Datasheet

Intel

E8870 Scalable Node Controller (SNC) Datasheet 8-3

System Reset

8.2.1 Power-up Reset Sequence

The following sections define the timing required of external E8870 chipset signals at power-up.

The power-up sequence is described in 3 phases: PWRGOOD deassertion, PWRGOOD assertion,

and hard reset deassertion. Each component must see this timing at power-up, although they may

not see the sequence at the same time. For example, if an SNC is hot-plugged, system logic on the

hot-plug module must drive the SNC RESETI# pin as specified, but the connected SPS will be out

of reset and operating normally.

Figure 8-1 shows the E8870 chipset power-up timing.

Figure 8-2 shows the timing for a hard reset deassertion.

Table 8-3 specifies the timings drawn in Figure 8-1 and Figure 8-2. Nominal clock frequencies are

described. Specifications still hold for de-rated clock frequencies.

Figure 8-1. Power-up Reset Timing

T1=10ms

PWRGOOD

RESETI#

Figure 8-2. Hard Reset Deassertion Timing

T12

ICH4 CPU_RST_DONE_ACK Sequence

RESETI#

CPU RESET# (if asserted)

Hard Reset De-Assertion

BNR# (if asserted for BINIT#)

MEMRST# (if asserted)

LPCRST#

Hub Interface to ICH4

RESET66#

T10