Datasheet

System Reset
8-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Table 8-3. Power-up and Hard Reset Deassertion Timings
Description Min Max Comments
T1 Power stable to PwrGood active 10ms As close to
10ms as
possible.
T3 PWRGOOD assertion to RESETI#
deassertion
1ms 2ms This delay can be provided
by system logic, or in non-
deterministic systems by the
ICH4.
T4 RESETI# deassertion to
RESET66#
deassertion
4002 SYSCLKs 4007 SYSCLKs Variation is due to alignment
of 66 MHz clocks and
SYSCLK.
T5 RESETI# deassertion to processor
RESET# deassertion.
200,000
SYSCLKs
200,000
SYSCLKs
Meets 1ms minimum Pulse
width.
T7 RESETI# deassertion to LRESET#
deassertion.
2
LPCCLKOUTs
10
LPCCLKOUTs
LPCCLKOUT is 25-33 MHz
clocks.
T9 RESET66# deassertion reset
sequence (SIOH to ICH4).
16 CLK66s 20 CLK66s 66 MHz.
T10 Hard reset deassertion to BNR
Throttle stops
3000/1500
BUSCLKs
3000/1500
BUSCLKs
BUSCLK is 200 MHz
Table 8-4. Critical Initialization Timings
Sequence Started By
Maximum Length
(200 MHz Clocks)
Covered by Timing
Parameter
SP Initialization in Half Speed
Mode Including Framing
Hard reset deassertion 2864 T5
SPS Snoop Filter initialization Redundancy download
complete
8000 T5
SNC Memory Array initialization Hard reset deassertion 128 T10
DRCG Lock Stable PCLKN and
SYNCLKN from SNC
800,000 Software
Initialization
LPC Stable LPCCLKOUT and
LRESET deassertion
4000 T5
SNC, SIOH Core clock PLL
capture time
PWRGOOD Assertion 1000 T3
SPS DLL Capture PWRGOOD Assertion 2000 T3
CLK66 PLL Capture First Hard reset dassertion 1000 T4
P64H2 PLL Capture CLK66 stable 6000 T4
Hub Interface Impedance
Compensation
CLK66 stable 1000 T5- T4
ICH4 CPURST Handshake RESET66# deassertion 300
SIOH Array initialization Hard reset deassertion 512 T5