Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-5
System Reset
8.2.1.1 PWRGOOD Deassertion
While PWRGOOD is deasserted, the SNC asserts RESET# to processors and LRESET# to the
LPC interface asynchronously.
The SIOH asserts RESET66# asynchronously.
Since internal clocks will not be within specifications while PWRGOOD is deasserted,
PWRGOOD must act asynchronously. All E8870 chipset components will reset any core logic that
can be asynchronously reset, and all logic must be forced into a non-destructive state. For example,
multiple drivers must not attempt to drive the same signal to different logic values. JTAG chains
and any logic clocked by TCK should be cleared. The TAP will not be operational until
PWRGOOD is asserted. TCK may or may not be active at this time. All outputs (except for any
reset outputs) are placed in a high impedance state.
RESETI# must be asserted when PWRGOOD rises.
If the E8870 chipset is operating, PWRGOOD can be deasserted to produce a total reset. In this
case power supplies and external clocks have been stable for more than 10ms, so PWRGOOD need
not be held inactive for more than 80ns.
8.2.1.2 PWRGOOD Assertion Sequence
RESETI# must be asserted by the system for 1ms after PWRGOOD rises to allow E8870 chipset
PLLs to lock. All logic in E8870 chipset components may be reset while RESETI# is asserted the
first time after PWRGOOD. Public JTAG chains and any logic clocked by TCK must be
operational (even though RESETI# is still asserted). Private JTAG chains need not be operational
while RESETI# is asserted.
SIOH should drive RESET66# to reset Hub Interface devices asynchronously.
The SNC continues to assert RESET# to processors until the first RESETI# deassertion.
8.2.1.3 First RESETI# Deassertion Sequence
SIOH should continue to drive RESET66# until T4 expires. Snoop Filter initialization is done next.
The first RESETI# deassertion after PWRGOOD is the synchronizing event for determinism.
RESETI# may or may not be distributed synchronously to 200 MHz core clock, but deassertion
must be detected by sampling with the 200 MHz internal core clock in each E8870 chipset
component.
References to clocks slower than 200 MHz generated by the E8870 chipset are reset by the first
RESETI# deassertion. The references must achieve their new phase ten clocks after the clock that
sampled the first RESETI# inactive. Any PLLs associated with those references may have to re-
capture. This does not imply that external clocks rise on the same picosecond. The important thing
is that when the slower clocks transfer data to the 200 MHz domain, the transfer occurs on the same
200 MHz edge on each reset and across different systems. Examples of slow clocks are
LPCCLKOUT, SPDCLK, SYNCLKN and PCLKN, and CLK66.
In the SNC, SPS, and SIOH, a modulo-8 counter is started on the first RESETI# deassertion. This
counter qualifies RESETI# sampling so that it is effectively sampled at 25 MHz. System logic is
allowed ~20ns (allowing for maximum 200 MHz clock skew between components and 5ns of
output delay + input setup) to distribute RESETI# to all components. Due to variation in clocks this
reset distribution, the counters in all components may not be in phase, but if the first RESETI#