Datasheet

System Reset
8-6 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
rising edge makes setup and hold at each component, the counters will all have the same phase
relationship on each power-up. Figure 8-3 shows how this sampling guarantees that RESETO#
from any SNC will produce the same hard reset deassertion phasings in each component.
The SNC starts a 240 cycle counter that is a multiple of the periods of all E8870 chipset clock
dividers that are not cleared on subsequent resets. The 240 cycle counter is not reset with
subsequent resets, staying in synch until PWRGOOD is asserted. When memory operations are
enabled in the SNC, the memory maintenance cycle is started when this counter=0. The memory
maintenance timer is also a multiple of 240 cycles, so it is also in phase with the clock dividers.
Subsequent RESETI# assertions can be deterministic if they are driven with fixed timing relative to
the memory maintenance cycle.
Hard Reset Deassertion Sequence Triggered
When RESETI# first rises, it triggers a hard reset deassertion sequence in all E8870 chipset
components. This sequence is described in Section 8.2.2.4. The first hard reset deassertion differs
from subsequent deassertions as follows:
• All sticky configuration bits are cleared. They may have already been cleared by PWRGOOD,
but clocks have been invalid since then. The inputs to sticky state must be masked to keep
them from latching invalid inputs produced during the reset sequence.
• Since the default value of SNC SYRE.SAVMEM is 0, the hard reset deassertion sequence in
the SNC is not delayed by the memory maintenance cycle.
Figure 8-3. Warm RESETI# Sampling
SNC Modulo-8
counter
0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SPS RESETI#
0 1 2 3 4
SNC RESETO#
RESETI#
Modulo 8 counters may
be out of phase due to
clock phase differences
and different number of
clocks in First RESETI#
distribution
Distribution Delay
Variation
Distribution Delay
Variation
0 1 2 3 4
HRDs asserted when
counters=1
When 2 metastability flops are
accounted for, RESETI# is
sampled when counters = 6
SNC drives
RESETO when
counters=0
00 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SPS Hard Reset
De-Assertion
SPS Modulo-8
counter
SNC Hard Reset
De-Assertion
SIOH Modulo-8
counter
SIOH Hard Reset
De-Assertion
1ms