Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-7
System Reset
8.2.2 Hard Reset
8.2.2.1 Hard Reset Assertion Sequence
•
RESETI# assertions need only be 80ns in width. Since hard reset assertion is a synchronous
response and core clocks are not valid during PWRGOOD, no hard reset assertion occurs in
the power-up sequence.
• Setting SYRE.SNCReset in SNC and SYRE.SIOHReset in SIOH.
• BINIT# assertion on SNC.
• Setting SYRE.HardReset configuration bits in the SNC.
Only the first hard reset assertion restarts clocks and clock references.
All logic that can be cleared in a single cycle may be cleared (for example flops with individual
resets, as opposed to arrays of non resetable storage that requires a sequencer to write 0’s to each
storage element in the array). Configuration bits are set to default values. Logic that remains
functioning through hard reset such as sticky configuration bits, SNC configuration protected by
SYRE.SAVCFG and Memory Maintenance Logic (when SYRE.SAVMEM is set) must not be
affected during hard reset. This logic must be protected from invalid inputs during reset. This
includes inputs from de-activated buses, initialization sequences, and spurious inputs on internal
interfaces. All operations initiated on the interface to this logic must be completed legally before
hard reset deassertion. The SNC will assert BNR# or RESET# on the processor bus until hard reset
deassertion and SPs will be disabled (if there are processors on the bus and Local firmware) to
support Itanium 2 processor BINIT#.
Logic that need not function through reset, (such as all logic in the SPS and SIOH, and all SNC
logic when neither SYRE.SAVCFG or SYRE.SAVMEM are set) may be held reset as long as
RESETI# is asserted.
Figure 8-4. Synchronization Point for Determinism
DivideBy3 reset by first
rising edge RESETI#
Transfers from slower domains are
synchronized to this point
533MHz PLLlock
200MHz PLLlock
CPU RESET#
Hard Reset De-Assertion
SNC,IOH,SPS PWRGD
RESETI#
All clock frequencies repeat the same
phasing at 240 (200MHz) clock
intervals
240 240 240 240 240 240 240 240
Mem Maintenance cycle started on
first 240 cycle boundary after MOE
Memory Maintenance Operation Enable (MOE)
RESETO#
SNC asserts RESETO# on Memory
Maintenance cycle boundaries with fixed
phase relative to clock alignments
240240
Memory Maintenance Cycle 100ms
Mem Maintenance cycle is
a multiple of 240 cycles