Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 1-7
Introduction
Implicit Write-Back (IWB) IWB is used to describe the hit-modified-snoop response to a
processor bus request. Although this is a response, it
modifies the handling of the original read. The new behavior
is independent of the original read type. In effect, the SNC
converts the original request into an IWB. A hit to a modified
line in the SIOH can also be called an IWB.
Inbound (IB)/Outbound (OB)
Upstream/Downstream,
Northbound/Southbound,
Upbound/Downbound
Up, North, or Inbound is in the direction of the processor.
Down, South, or Outbound is in the direction of I/O.
Line Cache line.
Local Requests that are initiated by processors on the same bus as a
given SNC.
Main Channel The RAC memory interface used by SNC.
Master Abort A response to an illegal request. Reads receive all 1’s data.
Writes have no effect.
Memory Data Quantum The smallest memory access for the E8870 chipset. Each of
the four main channels deliver 16B on an access. This 64-
byte quantity is a quanta. Memory error correction is applied
on a quantum basis.
MDFC Memory Device Failure Correction
Nodes Two uses: The first is in the context of the scalability port
agent, i.e. SNC, SPS or SIOH. The second refers to processor
nodes only (e.g. single node system).
Page Replace (Page Miss), Row
Hit/Page Miss
An access to a row that has another page open. The page
must be transferred back from the memory devices to the
array, and the bank must be precharged.
Page Hit An access to an open page, or DRAM row. For the Itanium 2
processor, the E8870 chipset makes two 64B accesses for a
cache line. The two halves of the cache line are always
placed on the same page, so that only one row command is
used. Outside of a cache line the E8870 chipset maps address
bits to optimize random accesses, at the expense of page hits.
Thus page hits outside a cache line are rare.
Page Miss (Empty Page) An access to a page that is not buffered in sense amps and
must be fetched from DRAM array.
RAMBUS ASIC Cell (RAC) It is the embedded cell designed by RAMBUS that interfaces
with the RAMBUS devices using RSL signaling. The RAC
communicates to the RMC.
Remote Requests that enter the SNC from a SP.
RSL RAMBUS signaling level is the name of the signaling
technology used by SNC on the main channel.
RCLK The period of the CTM and CFM clocks at 2.5 ns.
SEC/DED Single Error Correct/Double Error Detect
SIOH The Intel E8870IO server input/output hub: connects two
SPs to five hub interface ports.