Datasheet

System Reset
8-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
8.2.2.2 Hard Reset Assertion that Does Not Preserve Memory nor
Configuration
As the default value of SAVMEM is 0, power-up reset follows this path. Internal clocks are not
stable when PWRGOOD rises, so these actions are not guaranteed to immediately take effect.
However, the clocks will become stable long enough before RESETI# rises for these actions to
succeed. The SNC will respond to hard reset deassertion that does not preserve memory nor
configuration as follows:
• Assert RESET# and Power-on Configuration to the processor bus.
• Assert LRESET# and clear the FWH interface.
• The SNC holds all logic reset. Multi-cycle initialization does not start, so arrayed structures
are not yet initialized.
• The SPs are disabled.
• The SNC is ready to proceed to hard reset deassertion as soon as the deassertion trigger
arrives.
• No configuration bits are reset due to hard reset assertion.
8.2.2.3 Hard Reset Assertion that Preserves Memory or Configuration
The SNC will respond to hard reset deassertion that preserves memory or configuration as follows :
• New requests on the processor bus are blocked. The SNC asserts BNR# according to the
processor bus protocol. The SPs are disabled. If the reset is local to the SNC, this will hang
other chipset components. A hard reset that does not apply to all chipset components is not
continuable.
• No configuration bits are reset. Sticky bits may need to be protected from spurious changes
caused by initialization.
• The SNC may reset any logic not required to maintain memory or to complete memory
operations already initiated. The logic that tracks the DMH write queues is cleared, but any
operations already initiated must complete without violating DDR timing. Memory Scrubbing
logic should be reset.
• Assert LRESET# and clear the FWH interface.
• Any operations already initiated on main channel, and main channel serial interface are
completed correctly externally. A limited number of new operations stored in the SNC may be
initiated if that simplifies the design of the logic running through reset. All operations initiated
should be completed correctly.
• Memory maintenance operations such as current calibration, temperature calibration, and
refresh must continue through reset. The sequence of refresh banks is not disturbed.
• Delay hard reset deassertion until the memory maintenance cycle completes. If memory
maintenance operations are not enabled by SCC.MOE, the memory maintenance cycle is
completed every 240 cycles.
8.2.2.4 Hard Reset Deassertion Sequence
Whenever a hard reset deassertion is detected, all components begin to initialize their internal
structures. The timing of hard reset deassertion sequence is shown in Figure 8-2.