Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-9
System Reset
CLK66 and CLK33 references are reset only on the First Reset deassertion. After a delay to allow
CLK33 and CLK66 to stabilize, the SIOH deasserts RESET66# and initiates the ICH4 CPURST
handshake sequence. Subsequent resets have no effect on these clocks.
SP initialization and framing is started. SPs are enabled in all components except SNCs with local
firmware and processors attached. SP framing will not complete until software enables those SPs.
The SNC holds off processor requests. Unless BINIT# was the cause of the hard reset, the SNC
holds CPU RESET# and power-on-configuration for 1ms. If BINIT# was the cause, The SNC
toggles BNR# until the SNC completes multi-cycle initialization. MEMRST# is asserted to clear
any posted writes in the DMH. All multi-cycle initialization processes are started at this point.
Strapping pins (such as NODEID and BUSID) that are defined to be sampled when RESETI# rises,
are sampled.
When the hard reset deassertion sequence is complete, all logic should be initialized except for
sticky configuration bits and SNC configuration covered by SYRE.SAVMEM and
SYRE.SAVCFG. All logic associated with memory maintenance should be reset such that the
memory maintenance counter is not disturbed. Inputs from buses tristated during reset must be
masked until it is guaranteed that bus values are electrically and logically valid.
A hard reset deassertion will be re-triggerable within 50 clocks, as shown in Figure 8-5.
8.2.2.5 Hard Reset Deassertion
The SNC will respond to hard reset deassertion as follows:
• Release LRESET#.
• Release any resets on SNC logic held while RESETI# was asserted.
• Start SP initialization. The SPs are disabled if there is local firmware and processors present.
In that case SP framing will not complete until the SPs are enabled by software.
• If BINIT# caused the reset,
Toggle BNR#.
else
Clear non-sticky configuration register bits that are not protected by SYRE.SAVCFG or
SYRE.SAVMEM. This includes SYRE.SAVMEM and SYRE.SAVCFG. Software must
set these bits again for them to take effect on the next reset.
Assert RESET# and capture address bits in the CVCR register.
• Multi-cycle initialization processes are started. The LATT and RATT should be initialized
within 200 cycles. The data buffers need not be initialized. The SNC never reads a data buffer
before it is written.
Figure 8-5. Reset Re-triggering Limitations
RESETI#
Incomplete
Initialization
Complete Initialization
50 System Clocks