Datasheet

System Reset
8-10 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
• After Multi-cycle initialization is complete,
If ((MC.MT indicated DDR before the reset) OR
(this is the First Reset Deassertion after PWRGOOD)), Pulse MEMRST# to invalidate any
writes buffered in the DMH.
8.2.2.6 Deterministic Hard Reset
The E8870 chipset behavior following the first RESETI# deassertion will not necessarily be
repeatable. The E8870 chipset guarantees determinism only from resets triggered by a
configuration write to the system hard reset bit in the SNC SYRE register. First, software must set
the SYRE.SAVMEM configuration bit.
Preserving Memory
If SYRE.SAVMEM is set (and memory maintenance operations are enabled SCC.MOE), the SNC
will maintain memory through RESETI# assertions. Hard reset deassertion will clear this bit, so it
must be set each time a deterministic reset is required. Software then sets the SNC system hard
reset configuration bit. RESETO# is driven from a flop enabled by the modulo-8 counter that
samples RESETI#. The system routes RESETO# to RESETI# in the SNC, and RESETI# to SIOH.
SPS and SIOH perform their hard reset deassertion sequences when RESETI# is deasserted, but the
SNC does not begin its hard reset deassertion sequence until the memory maintenance cycle is
complete. Memory maintenance operations continue while RESETI# is asserted.
Up to 72 writes may be dropped in the SNC and DMH unless flushed by software.
Figure 8-6. Deterministic Hard Reset Timing
100ms memory maintenance cycle
RESETI#
SNC,IOH,SPS Hard Reset Assertion
SPS, IOH Hard Reset De-Assertion
100ms memory maintenance cycle
RESETO#
SYRE.SysHardReset
RESET# to processors (if driven)
100ms memory maintenance cycle
SNC Hard Reset De-Assertion
BNR# (if RESET# driven)
BNR# (if driven instead of RESET#)