Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-11
System Reset
DDR-SDRAM refresh is not synchronized to the memory maintenance cycle. The DDR refresh
counter in the SNC will be cleared on hard reset deassertion to maintain determinism. In the worst
case, this can double one refresh interval. Since refreshes rotate across the 16 possible DIMM
sides, a given DIMM side may experience a refresh interval 17/16
ths
longer than usual. To
guarantee that each DIMM side receives one refresh every 15.6 us, the refresh rate must be set 17/
16 higher than required by DDR specifications. Writes buffered in the DMH and the corresponding
timing conflict trackers in the SNC will be cleared on hard reset deassertion.
If the SYRE.SAVMEM configuration bit is set, the SNC hard reset deassertion sequence starts at
the end of the memory maintenance cycle, the determinism synchronization point. BNR# is
toggled until the end of the next memory maintenance cycle. At that point, a hard reset deassertion
response starts. Unless BINIT# was the cause of the reset, BNR# is deasserted and RESET# is
asserted to the processors. If BINIT# was the cause of reset, BNR# is toggled instead. In either
case, the first processor request, which initiates all system activity, occurs with fixed timing
relative to all E8870 chipset clocks.
Non-deterministic Hard Resets
Since a hot-plugged component does not get the same synchronization point as the rest of the
system, deterministic operation is not possible after it is brought on-line. The hot-plugged
component never received the same synchronization point as the rest of the system. Only a Power-
up Reset Sequence can provide this synchronization point.
If the SYRE.SAVMEM bit is not set in the SNC, memory maintenance operations are not enabled,
the RESETI# is not delivered synchronously, or the reset is not triggered by SNC
SYRE.SysHardReset configuration bit, the E8870 chipset operates as previously described, but
determinism is not guaranteed. The Hard Reset Assertion and Hard Reset Deassertion sequences
remain the same.
8.2.2.7 Local Resets
Local Resets clear some E8870 chipset components but not others. If there are any outstanding
transactions, the portion of the E8870 chipset system that is not reset will hang. If system operation
is expected to continue, software must guarantee that all transactions are complete.
The SNC Reset bit in the SYRE register initiates a hard reset sequence in the SNC, which will reset
processors and the LPC interface. This bit will be reset when the hard reset deassertion sequence is
complete. This reset is delayed long enough to allow an SP configuration write that sets the bit to
complete in the idle case.
The SIOH Reset bit in the SYRE register initiates a hard reset sequence in the SIOH, which will
reset all Hub Interfaces. This reset is delayed long enough to allow an SP configuration write that
sets the bit to complete in the idle case.
Processor-only resets clear some E8870 chipset components but not others. If there are any
outstanding transactions, the portion of the E8870 chipset system not reset will hang. If system
operation is expected to continue, software must guarantee that all transactions are complete. A
processor only reset preserves E8870 chipset configuration through reset. SYRE.SAVCFG is
cleared by RESETI# assertions, so it must be set before each write to the system hard reset bit in
the SNCs SYRE register.
Whenever an SP is reset, both sides of the bus re-initialize.