Datasheet

System Reset
8-12 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
8.2.2.8 Itanium
®
2 Processor BINIT# Reset
A BINIT# assertion on the Itanium 2 processor bus triggers a hard reset assertion sequence
followed by a hard reset deassertion sequence in the SNC. The hard reset assertion sequences
results in the processor and SP buses being blocked while outstanding memory accesses are
completed. RESET# and associated processor power-up configuration values are not driven. BNR#
is deasserted when the memory maintenance cycle is complete. Local memory and local flash will
be accessible after the sequence completes. This enables the processor to dump state into local
memory. Only local memory access is possible following a BINIT#. Continued machine check
operation after BINIT# is not supported on systems with no local flash.
Resetting the SNC during normal operation will hang the remainder of the system. In order to store
the memory image to disk, software must set the SYRE.SAVMEM bit which was cleared by the
BINIT hard reset deassertion. Then it must initiate a reboot by setting the system hard reset bit in
the SNC SYRE register. Providing that SYRE.SAVMEM was set in all SNCs of the system during
reboot, the memory image may be saved to disk.
8.2.3 Soft Reset
If the SNC SYRE.SoftReset configuration bit is set, INIT# is asserted
8.2.4 Software initialization
8.2.4.1 SNC SPs
On an SNC that has working processors and local firmware present, the SPs will come up disabled.
Once the node completes node boot, software will enable the SPs, and the framing process will
complete.
8.2.5 Memory after Hard Reset
Software need not re-initialize memory after a reset when the SNC SYRE.SAVMEM bit is set. If
SAVMEM is not set, the memory must be initialized as it was for power-up. Any software using
this feature must remember that memory has been initialized through a reset; the SNC will provide
no indication.
8.3 Reset Signals
The E8870 chipset signals that are involved in reset are summarized in the following sections. The
timing of these signals is described in Section 8.2, “Reset Sequences.”
PWRGOOD will be deasserted as the voltage supplies come up, or may be pulsed after power-on
to clear the system. The assertion of the PWRGOOD signal indicates that external clocks and
power at the particular E8870 chipset component is stable.
Figure 8-7 provides an example of the simplest power-good signal distribution. It is not necessary
that the PWRGOOD signal is distributed in this fashion. For example, hot-plug considerations may
require each SNC to have a separate PWRGOOD signal. Figure 8-1 shows the required timing.