Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-13
System Reset
8.3.1 ICH4: PWROK
This pin causes the ICH4 to assert PCIRST#. It may be connected to PWRGOOD pins of all E8870
chipset components (as illustrated in Figure 8-7), or the result of an OR of PWRGOOD, SNC
RESETO# pins, or other sources of hard reset (as illustrated by Figure 8-8). PWROK must be
delayed until SIOH clocks to the ICH4 are stable.
8.3.2 Basic Reset Distribution
Figure 8-8 shows an example on the reset distribution of an E8870 chipset system. The ICH4 will
generate PCIRST# from either PWRGOOD or writes to certain registers. This PCIRST# will be
buffered and distributed to each component’s RESETI#. The SIOH generates RESET66# on each
Hub Interface, and the SNC generates RESET# to processors, MEMRST#, and LRESET#.
8.3.3 SIOH: DET
The DET pin is strapped high to enable determinism in the E8870 chipset. If high, CLK33 and
CLK66 references are reset on first hard reset deassertion as described in Section 8.2.2.4, “Hard
Reset Deassertion Sequence”. If this pin is low, the dividers that provide references for these clocks
can come up at an arbitrary phase relative to the same clocks on other SIOHs and SNC memory
maintenance operations.
8.3.4 ICH4: PCIRST#
ICH4 will drive PCIRST# for a minimum of 1ms after the deassertion of its PWROK pin or when the
hard reset sequence is initiated through the CF9 I/O register. For non-deterministic systems, this may
be connected to RESETI# of the SNC, SIOH, and SPS.
Figure 8-7. Simplest Power Good Distribution
SPSs SNCs
Processors
SIOHs
ICH4s
Power Good
Logic
DMHs
PWRGOODPWRGOODPWRGOODPWRGOOD
PWRGOOD
PWROK
DET