Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-15
System Reset
8.3.6 SIOH: RESET66#
This pin is asserted combinationally while RESETI# is asserted or asynchronously after
PWRGOOD assertion, or if the hard reset bit is set in the SIOH SYRE register. RESET66# will rise
synchronously to CLK66. This pin will be driven to the P64H2 RSTIN# pin.
8.3.7 P64H2: RSTIN#
The SIOH drives this with RESET66#. All P64H2 logic is cleared synchronously when RSTIN# is
asserted.
8.3.8 SNC: RESETO#
The SNC drives its RESETO# pin after the system hard reset bit in the SYRE register is written. It
does not reset the SNC or any other E8870 chipset logic. RESETO# assertion is delayed until the
Memory Maintenance Cycle completes so that resets are synchronized with memory maintenance
operations.
8.3.9 SNC: RESET# and Processor Power-on Configuration
The SNC drives the RESET# pin on the processor bus to hard reset the processors. The SNC drives
power-on configuration from its CVDR register to certain processor bus address lines while this
signal is asserted.
The SNC drives the RESET# signal asynchronously on this interface while PWRGOOD is
deasserted.
After PWRGOOD is asserted, RESETI# will be asserted; RESET# is still driven asynchronously.
When RESETI# is deasserted, RESET# is deasserted synchronous to BUSCLK.
8.3.10 SNC and DMH: MEMRST#
The SNC asserts MEMRST# to the DMH. It is pulsed just as RESETI# is deasserted. MEMRST#
clears posted writes inside the DMH, so when memory is present, it is pulsed on every SNC Hard
Reset De-assertion.
8.3.11 SNC and DMH: R[3:0]SCK,R[3:0]SIO,R[3:0]CMD
The SNC holds SCK in reset until RESETI# is deasserted. After that it toggles at 1 MHz. Firmware
initializes the DMH through this interfaces.
8.3.12 SNC: LRESET#
The SNC asserts LRESET# to the LPC/FWH port. It is driven active while RESETI# is asserted
and deasserted synchronous to LPCCLKOUT after SNC hard reset deassertion. LRESET# must be
driven active for at least 100ns and no LPC access must occur for 20us.