Datasheet

System Reset
8-16 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
8.3.13 SNC: BNR#
The SNC toggles BNR# to prevent requests from being initiated on the processor bus until the
E8870 chipset initialization is complete.
8.3.14 SNC: BINIT#
In the SNC, this pin initiates the reset described in Section 8.2.2.8, “Itanium
®
2 Processor BINIT#
Reset”.
8.3.15 SNC: INIT#
Asserting the INIT# signal to the processors forces them to start execution at the boot vector. The
SNC provides an INIT# output that is asserted when the Soft Reset bit in the SYRE register is set.
System logic should combine the SNC INIT# signal with INIT# signals from other sources (such
as the ICH4), and drive the result to the processors.
The SNC does not respond to INIT# assertion.
8.3.16 P64H2: CLK66,PXPCLKO,PXPCLKI
The P64H2 gets 66 MHz phasing information from the SIOH CLK66. The P64H2 uses these and
the 200MHz to produce a 66 MHz internal clock that is in phase with CLK66. This is phase locked
to the P64H2 core clock which is locked to the PxPCLKO. This is distributed to the PCI devices.
PxPCLKI is delay matched by system logic so that it arrives at the P64H2 at the same time as it
arrives at the other devices on the bus. The P64H2 supports a mode in which the skew between
CLK66 and PxPCLKI is controlled. Synchronous transfers can be made between the Hub Interface
domain and PCI domain.
8.3.17 SIOH: CLK33
This clock is CLK66 divided by two. The system must control CLK33 routing delays between
SIOH and ICH4 in order to meet ICH4 clock phasing requirements.
8.3.18 SNC and SPS and SIOH: NODEID,BUSID
These straps are sampled as RESETI# deasserted.