Datasheet

Introduction
1-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
1.6 References
The reader of this specification should also be familiar with material and concepts presented in the
following documents:
• IEEE 1149.1a-1993
• Jedec Standard 79 (JESD79)
• PCI Local Bus Specification, Rev. 2.2
• Intel
®
Itanium
®
2 Processor Datasheet
• Intel
®
E8870IO Server I/O Hub (SIOH) Datasheet
• Intel
®
E8870DH DDR Memory Hub (DMH) Datasheet
• Intel
®
82802AB/82802AC Firmware Hub (FWH)
• LPC Interface Specifications, Rev. 1.0
1.7 Revision History
SNC Scalable Node Controller. This chipset component interface
with the Itanium 2 processor, main memory, and SP links.
SPS Intel E8870SP Scalability Port Switch. The crossbar/central
snoop filter that connects the SNCs and SIOHs.
SPP Scalability Port Protocol Logic. The SNC cluster that
controls sequencing of coherent requests.
SSO Simultaneous Switching Output
System Bus A generic term used to refer to the Itanium 2 processor
system bus (128 bits wide).
Virtual Channel Requests and responses on the SP are time multiplexed on
the SP wires, but separate flow control is provided so that
one channel makes progress even if the other is blocked. The
logical effect is as if there were separate “virtual channels”
for requests and responses.
DEN#,HITM#,ADS#,A[44:0]# Processor bus signals.
Revision
Number
Description Date
-001 Initial release of this document. August 2002