Datasheet

Electrical Specifications
9-2 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
9.3 SNC System Bus Signal Group
9.3.1 Overview
In this section, the system bus signals relevant to the SNC are outlined.
SNC system bus interface signals use the Itanium processor’s AGTL+ (assisted gunning
transceiver logic) signaling technology. The termination voltage, VTTMK, is generated on the
baseboard and is the system bus high reference voltage. The buffers that drive most of the system
bus signals on the SNC are actively driven to VTTMK during a low-to-high transition to improve
rise times and reduce noise. These signals should still be considered open-drain and do require
termination to VTTMK.
The system bus is terminated to VTTMK through active termination within the bus agents at each
end of the bus. VTTMK specification is outlined in the Power section, see Table 9-2.
Memory main channel Interface
VCCRIO Termination Voltage 1.71 1.8 1.89 V
Irio Termination Current 650 mA
h
dIrio/dt Transient Slew Rate 0.025 A/ns
Scalability Port Interface
i
VCCSP
Scalability Port Supply
Voltage
1.209 1.30 1.391 V
j,k,l
Isp Scalability Port Current 0.50 A
m,n
dIsp/dt Transient Slew Rate 1.0 A/ns
o
LPC and I
2
C
Vcc3.3lpc,VccI2C LPC and I
2
C Voltage 3.135 3.3 3.465 V
p
Iv LPC and I
2
C Current 140 230 mA
dIv/dt
LPC and I
2
C Transient
Current
0.35 0.55 A/ns
q
a. Core voltage for SNC.
b. Specification comprehends all AC and DC components.
c. The maximum ICC current is the worst case specification, (i.e. Vcc max, low temperature and application mix) intended for
power supply design.
d. Itt max can be calculated from Ron (min) at Vol (max).
e. Only applies to the SNC terminating and not the entire processor’s system bus termination current requirement.
f. The on-die Rtt is measured at Vol of the AGTL+ output driver. Refer to component I/O buffer model for I/V curve.
g. ODT (on-die termination) nominal value is driven from the externally installed resistor, 86.7 Ohm resistor at 1%, 0.1W, or
better, across the FSBODTCRES0 and FSBODTCRES1 pins.
h. Specification is per main channel.
i. Estimated values provided for power budgeting considerations; these parameters are not tested. This is the same SP inter-
face as specified in SIOH and SPS.
j. Vccsp budget is ±3% DC, and (DC + AC) at ±7% noise delivered at the pin.
k. The power pins are separated at the package from the Vcc core or other supplies on-die.
l. The power supply must be local to each component. The SP power supply between two communicating ports needs to be
separate.
m. The current requirement per scalability port (SP) port.
n. Under normal operating conditions. However, under certain test conditions, Isp might exceed the specification.
o. The specification is per SP port at the package pin.
p. Two pins can be tied together on the motherboard.
q. I
2
C circuitry does not contribute significantly to the 3.3V transient load.
Table 9-2. Voltage and Current Specifications (Continued)
Symbol Parameter Min Typical Max Unit Notes