Datasheet
Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 9-3
Electrical Specifications
AGTL+ inputs use differential receivers which require a reference signal (Vref). The SNC
generates Vref on-die so there is no need for external logic.
9.3.2 Signal Group
Table 9-3 contains the SNC system bus signals that are combined into groups by buffer type and
whether they are inputs, outputs, or bidirectional with respect to the SNC.
Most of the system bus signals use assisted gunning transceiver logic (AGTL+) signaling
technology. This signaling technology provides improved noise margins and reduced ringing.
AGTL+ output signals require termination to VTTMK. In this section, “AGTL+ Input Signals”
refers to the AGTL+ input group, as well as the AGTL+ I/O group when receiving. Similarly,
“AGTL+ Output Signals” refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
The SNC system bus interface signal pins are terminated via on-die termination to VTTMK supply
voltage, so no external termination resistor is required.
The system bus clock signals are LVHSTL, which are compatible with the Itanium 2 processor
differential clock inputs. All miscellaneous and clock signals are documented in Section 9.8 and
Section 9.9.
.
Table 9-3. SNC System Bus Signal Groups
Signal Group Signal
AGTL+ Output Signals
BPRI#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET#, RS[2:0]#, RSP#,
TRDY#
AGTL+ I/O Signals
A[43:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]#, BREQ0#,
D[127:0]#, DBSY#, DRDY#, DEP[15:0]#, DRDY#, HIT#, HITM#, REQ[5:0]#,
RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND#
AGTL+ Input Signals BREQ[3:1]#, LOCK#
Special AGTL+ Asynchronous
Output Signals
INIT#
Power/Other
a
a. The SNC generates system bus Vref on-die.
VCC
b
, VTTMK
c
, VSS
b. SNC core voltage. See Table 9-2.
Analog Input
d
VCCAFSB
e
, VSSAFSB, FSBSLWCRES[1:0]
f
, FSBODTCRES[1:0]
g
Signals Associated Strobe
REQ[5:0]#,A[49:3]# ADS#
D[15:0]#, DEP[1:0]# STBP[0]#, STBN[0]#
D[31:16]#, DEP[3:2]# STBP[1]#, STBN[1]#
D[47:32]#, DEP[5:4]# STBP[2]#, STBN[2]#
D[63:48]#, DEP[7:6]# STBP[3]#, STBN[3]#
D[79:64]#, DEP[9:8]# STBP[4]#, STBN[4]#
D[95:80]#, DEP[11:10]# STBP[5]#, STBN[5]#
D[111:96]#, DEP[13:12]# STBP[6]#, STBN[6]#
D[127:112]#, DEP[15:14]# STBP[7]#, STBN[7]#