Datasheet
Electrical Specifications
9-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
9.3.3 DC Specifications
The DC specifications for all the system bus interface signals are contained in Table 9-4.
9.4 Scalability Port (SP) Signal Group
The SP interface is a source-synchronous interface with coincident data and continuous strobe
transmission. The data and strobe signals are launched simultaneously and are expected to arrive at
the receiver with the same timing relationship to one another.
Each SP port consists of two strands that are further subdivided into two bundles. Each SP port
consists of 32 data bits, 4 ECC bits, 2 parity bits, 2 SSO coding bits, 2 link layer control (LLC) bits,
4 strobe pairs (8 signal pins), reserved pins, and 8 reference voltage pairs (16 signal pins).
The simultaneous bi-directional (SBD) signaling can create conditions for three logic levels on the
interconnect (0, 0.65, 1.3)V, depending on the data values driven from each end of the trace.
All SBD signals are terminated via on-die termination. The reference voltages are generated on die
and are set to 1/4VCCSP and 3/4VCCSP, so no external logic is needed to generate these reference
voltages.
Each SP voltage reference pin is required to be interlinked to the corresponding SP port.
Table 9-5 summarizes the signal grouping of the SP interface. The “x” in the signal names is
replaced with the specific SP port on the SIOH (0 or 1).
c. VTTMK, the system bus termination voltage. See Table 9-2.
d. PLL analog voltage input.
e. Connect to 1.5V ±5% supply on the motherboard through a network filter.
f. Connect 1K Ohm, 1%, 0.1W, resistor across the FSBSLWCRES0 and FSBSLWCRES1.
g. Connect 86.7 Ohm 1%, 0.1 W, resistor across the FSBODTCRES0 and FSBODTCRES1.
Table 9-4. SNC AGTL+ DC Parameters
a,b
a. All specifications are at the pin of the package.
b. Parameters applies to input, output and I/O buffer.
Symbol Parameter Min Max Unit Notes
Vil Input Low Voltage 0.585 V
c
c. All specifications are measured into a 50-ohm test load connected to 1.2V.
Vih Input High Voltage 0.915 V
c
Vol Output Low Voltage 0.40 V
c
Voh Output High Voltage 1.05 V
c
Iol Output Low Current 17 mA
Ili Input Leakage Current 50 µA
C
AGTL+
AGTL+ Pin Capacitance 2.8 4.0 pF
Table 9-5. Scalability Port Interface Signal Group
Signal Signal Description
SBD I/O SPxAD[15;0],SPxBD[15;0], SPxASTBP[1:0], SPxASTBPN[1:0],
SPxBSTBP[1:0], SPxBSTBPN[1:0], SPxAEP[2:0], SPxBEP[2:0], SPxALLC,
SPxBLLC, SPxASSO, SPxBSSO
CMOS1.5 I/O OD
a
SPxGPIO[1:0]