Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 9-5
Electrical Specifications
9.5 Main Channel Interface
9.5.1 Main Channel Interface Reference Voltage Specification
CMOS1.3 INPUT
a
SPxPRES
CMOS1.3 I/O
a
SPxSYNC
Power/Other VCCSP
b
, VSS
Analog I/O
c
SPxZUPD[1:0]
d
, SPxAVREFH[3:0], SPxBVREFH[3:0], SPxAVREFL[3:0],
SPxBVREFL[3:0]
e
SP Analog Input VCCASP
e
, VSSASP
a. See Section 9.8 for “CMOS1.3” specifications.
b. VCCSP is to be supplied to the SP port externally. See Tab le 9- 2.
c. Reference voltages are generated on-die.
d. SPxZUPD0 impedance update pins are connected through a 45-ohm, 1% resistor to Vccsp; SPxZUPD1 impedance update
pins are connected through 45-ohm, 1% resistor to Vss.
e. PLL analog voltage for SP, connected on the motherboard to Vcc15 supply (1.5V nominal ±5%) through a filter network.
Table 9-6. DMH Main Channel Signal Groups
Signal Group Signal
RSL I/O Pins R{0/1/2/3}DQA[8:0], R{0/1/2/3}DQB[8:0]
RSL Input Pins R{0/1/2/3}RQ[7:0], R{0/1/2/3}CFM, R{0/1/2/3}CFMN (differential clock)
RSL Input Pins R{0/1/2/3}CTM, R{0/1/2/3}CTMN (differential clock)
CMOS 1.8 Output Pins
a
a. See Tab le 9- 23 and Table 9-29 for “CMOS 1.8” specification.
R(0/1/2/3}SCK, R{0/1/2/3}CMD, R{0/1/2/3}SYNCLKN, R{0/1/2/3}PCLKM
CMOS 1.8 I/O Pins
b
b. See Table 9-10 for “CMOS 1.8 I/O” specification.
R{0/1/2/3}SIO
Power/Other VCCRA, R{0/1}VREF[1:0]
c
, VSS
c. See Tab le 9 -7 for Vref specification.
Table 9-7. Main Channel Vref Specification
Symbol Parameter Min Typical Max Units Notes
Vref,r Main Channel Reference Voltage 1.25 1.40 1.53 V
a
a. Vref is generated from 1.8V voltage (VCCRIO on the SNC).
Table 9-5. Scalability Port Interface Signal Group (Continued)
Signal Signal Description