Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 9-7
Electrical Specifications
9.6 LPC Signal Group
The seven required and five supporting signals used for the low pin count (LPC) interface are listed
in the following table. Many of the signals are the same as signals found on the PCI interface.
9.6.1 DC Specifications
9.6.2 AC Specifications
For a complete LPC data sheet including AC specifications and timing relationships, refer to the
Low Pin Count (LPC) Interface Specification.
9.7 SMBus and TAP Electrical Specifications
The SNC uses open-drain outputs and has its own defined logic levels, which are different than
CMOS logic levels.
The TAP connection input signals require external termination. No reference voltage is required for
these signals.
The SMBus and TAP signals require termination to 3.3V and 1.5V on the motherboard,
respectively.
Table 9-11. LPC Interface Signal Group
Signal Group Signal
LPC I/O LAD[3:0]
LPC Output LFRAME#, LRESET#, LPCCLKOUT[2:0]
LPC Input LCLK
CMOS 1.5 Input
a
a. See Section 9.8 for CMOS 1.5V specifications.
LPCSEL, LPCEN
Table 9-12. LPC DC Parameters
a,b
a. All specifications are at the pin of the package.
b. Parameters apply to LPC inputs, outputs, I/O buffers and clock output.
Symbol Parameter Min Max Unit Notes
Vil Input Low Voltage 0.99 V
Vih Input High Voltage 1.65 V
Vol Output Low Voltage 0.33 V
c
c. At 1.5 mA minimum.
Voh Output High Voltage 2.97 V
d
d. At -0.5 mA minimum.
CkVol Clock Output Low Voltage 0.66 V
c
CkVoh Clock Output High Voltage 1.98 V
d
I
li
Input Leakage Current 150 µA
e
e. Requires external 10k ohm pull-up resistor.
CClk Clock Input Capacitance 0.5 10 pF