Datasheet

Electrical Specifications
9-10 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
9.7.3 AC Timing Waveforms
The following figures are used in conjunction with the AC timing Table 9-13 and Table 9-14.
Note: The following apply:
1. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 • Vcc_tap at the
component pin. All TAP signal timings (TMS, TDI, etc.) are referenced at the package pin.
2. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 • SM_Vcc
at the component pin. All SMBus signal timings (SM_DAT, SM_ALERT#, etc.) are
referenced at 0.5 • SM_Vcc at the package pin.
Table 9-18. TAP Signal Group AC Specifications
a
a. All AC timings for the TAP signals are referenced to TCK at 50% voltage level.
Symbol Parameter Minimum Maximum Unit Figure Notes
TCK Frequency 1.0 20 MHz 9-3
T58
TCK, TMS, TDI Rise
Time
0.5 16 ns 9-3
b
b. Rise and fall times are measured from the 20% to 80% points of the signal swing.
T59 TCK, TMS, TDI Fall Time 0.5 16 ns
b
TDO Rise Time 2.3 4.6 ns
b
TDO Fall Time 1.2 5.3 ns
b
T60
TDO Clock to Output
Delay
2.5 10 ns 9-2
c
c. Referenced to the falling edge of TCK.
T61 TDI, TMS Setup Time 5 ns 9-2
d,e
d. Specification for a minimum swing defined between TAP V IL_MAX to V IH_MIN. This assumes a minimum edge rate of
0.5V per ns.
e. Referenced to the rising edge of TCK at the component pin.
T62 TDI, TMS Hold Time 18 ns 9-2
d,e
TRST# Assert Time 300 ns
Figure 9-2. TAP and SMBus Valid Delay Timing Waveform
T
x
= T60 (Valid Time)
T
a
= T61 (Setup Time)
T
h
= T62 (Hold Time)
V = 0.5* SM_Vcc for SMBus Signal Group
Clock
Signal
T
x
T
s
T
h
Valid
V