Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 2-1
Signal Description 2
2.1 Conventions
The terms assertion and deassertion are used extensively when describing signals, to avoid
confusion when working with a mix of active-high and active-low signals. The term assert, or
assertion, indicates that the signal is active, independent of whether the active level is represented
by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive.
Signal names may or may not have a “#” appended to them. The “#” symbol at the end of a signal
name indicates that the active, or asserted state occurs when the signal is at a low voltage level.
When “#” is not present after the signal name the signal is asserted when at the high voltage level.
When discussing data values used inside the component, the logical value is used. For instance.,a
data value described as “1101b” would appear as “1101b” on an active-high bus, and as “0010b”
on an active-low bus. When discussing the assertion of a value on the actual signal, the physical
value is used; i.e. asserting an active-low signal produces a “0” value on the signal.
Table 2-1 and Table 2-2 list the reference terminology used later for buffer technology types (e.g.
LVTTL, etc.) used and buffering signal types (e.g. input, output, etc.) used.
Table 2-1. Buffer Technology Types
Buffer Buffer Type Description
AGTL+ 1.2 V Open drain Advanced GTL+ interface.
SBD 1.3 V Simultaneous Bi-Directional.
Differential LVHSTL
Itanium
®
2 processor-based system low voltage differential
input clock.
CMOS1.3 1.3 V CMOS, push/pull, type I/O or I.
CMOS1.5 1.5 V CMOS, push/pull, type I/O or I.
CMOS3.3 3.3V CMOS, push/pull, type I/O or I.
CMOS1.5OD 1.5 V Open-Drain CMOS type I/O.
CMOS3.3OD 3.3 V Open-Drain CMOS type I/O.
CMOS1.8 1.8 V CMOS, push/pull, type I/O.
RCMOS1.8 1.8 V
CMOS, push/pull, type I/O or O. No boundary scan on output,
boundary-scan only on input in the main channel interface.
LPC LPC
LPC I/O input with a voltage level of 3.3V and max. frequency of
33 MHz.
RSL RSL
High-speed (800 MHz) RAMBUS ASIC Cell (RAC) I/O with
differential inputs. XOR-tree instead of boundary-scan.
SSTL_2 SSTL-2 DDR bus interface signal type.
JTAG JTAG
Open-drain CMOS type I/O at 1.5V, without boundary scan
logic.
Analog Analog Typically a voltage reference or specialty power supply.