Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 9-15
Electrical Specifications
9.9 Clock Signal Groups
9.9.1 AC Specification
SRf Output Slew Rate Fall 1 4 V/ns
SRr Output Slew Rate Rise 1 4 V/ns
a. Supply voltage at 1.5V ±5% tolerance.
b. Clock delay is in reference to the 200 MHz clock.
Table 9-31. Clock Signal Groups
Signal Group Signals
LVHSTL Differential Inputs BUSCLK, BUSCLK#
Table 9-32. LVHSTL Clock DC Parameters
Symbol Parameter Min Typ Max Unit
V
IH
Input High Voltage 0.78 1.3 V
V
IL
Input Low Voltage –0.3 0.5 V
V
X
Input Crossover Voltage 0.55 0.85 V
C
CLK
Input Capacitance 1.0 11.5 pF
Table 9-33. LVHSTL Differential Clock AC Specification
Symbol Parameter Min Typ Max Unit Notes
T
period
BUSCLK Period 5.0 ns
a
a. See Figure 9-4.
f
BCLK
BUSCLK Frequency 200 200 MHz
a,b
b. Measured on cross point of rising edge of BUSCLK and falling edge of BUSCLK#. Long term jitter is defined as peak-to-peak
variation measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
T
jitter
BUSCLK Input Jitter 100 ps
a,c
c. Long term jitter is defined as peak-to-peak variation measured by accumulating a large number of clock cycles and recording
peak-to-peak jitter.
T
high
BUSCLK High Time 2.25 2.5 2.75 ns
a,d
d. Measured on cross point of rising edge of BUSCLK and falling edge of BUSCLK#.
T
low
BUSCLK Low Time 2.25 2.5 2.75 ns
a,d
T
rise
BUSCLK Rise Time 333 500 667 ps
a
T
fall
BUSCLK Fall Time 333 500 667 ps
a
V
PP
Minimum Input Swing 600 mV
a,e
e. V
PPmin
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
Table 9-30. CMOS 3.3 V AC Parameters
a,b
(Continued)
Symbol Parameter Min Max Unit Notes