Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 2-3
Signal Description
Main Channels 0, 1, 2, 3 (continued)
R{0/1/2/3}EXCC
O
RSL
800 MHz
Column Expansion Signal
These signals are not used by SNC.
R{0/1/2/3}CTM
I
RSL
400 MHz
Clock to Master
One of the two differential transmit clock signals used for RDRAM
operations on the corresponding RAMBUS channel. It is input to
SNC and is generated by an external clock generator.
R{0/1/2/3}CTMN
I
RSL
400 MHz
Clock to RAMBUS Master Complement
One of the two differential transmit clock signals used for RDRAM
operations on the corresponding RAMBUS channel. It is
complement of clock signal R{0/1/2/3}CTM.
R{0/1/2/3}CFM
O
RSL
400 MHz
Clock from Master
One of the two differential signals used to clock RAMBUS packets
driven by the SNC. These signals are of type I/O in the RTL as
defined by RAMBUS.
R{0/1/2/3}CFMN
O
RSL
400 MHz
Clock from Master Complement
One of the two differential signals used to clock RAMBUS packets
driven by the SNC. These signals are of type I/O in the RTL as
defined by RAMBUS.
R{0/1/2/3}SYNCLKN
O
RCMOS1.8
33 MHz
Phase Detect Signal
This signal is sent to DRCG for generating 400 MHz clock. This
signal is generated from SYNCLKN of the corresponding RAC.
This signal trace must be delay matched with R{0/1/2/3}PCLKM
trace.
R{0/1/2/3}PCLKM
O
RCMOS1.8
33 MHz
Phase Detect Signal
This signal is sent to the DRCG for generating the 400 MHz clock.
This signal is generated from the SNC core clock.
R{0/1/2/3}SCK
O
RCMOS1.8
1 MHz
or
100 MHz
Serial Clock
Clock source used for timing of the R{0/1/2/3}SIO and R{0/1/2/
3}CMD signals.
R{0/1/2/3}SIO
I/O
RCMOS1.8
1 MHz
or
100 MHz
Serial Input/Output Chain
Bi-directional serial data signal used for reading and writing control
registers.
R{0/1/2/3}CMD
O
RCMOS1.8
1 MHz
or
100 MHz
Serial Command
Serial command input used for control register read and write
operations.
R{0/1/2/3}VREF[1:0]
I
Analog
N/A
Voltage Reference
Supplies Vref for input buffers.
Scalability Port 0, 1
SP{0/1}ZUPD[1:0]
I
Analog
N/A
Impedance Update
Used to adjust the impedance of I/O drivers CMOS1.5
SP{0/1}SYNC
I/O
CMOS1.3
N/A
Reset Synchronization
Provides synchronization between ports for impedance control and
reference voltage adjustment. This signal is also used by the SP
reset logic to determine when SP comes out of reset.
SP{0/1}SYNC is released when ports at both ends of the link are
ready.
SP{0/1}PRES
I
CMOS1.3
N/A
Scalability Port Present
Signals the scalability port of an impending hot plug event
SP{0/1}AVREFH[3:0]
I/O
Analog
N/A
Strand A Voltage reference
3/4 VCC-SP Reference
SP{0/1}AVREFL[3:0]
I/O
Analog
N/A
Strand A Voltage Reference
1/4 VCC-SP Reference
SP{0/1}ASTBP[1:0]
I/O
SBD
400 MHz
P Strobes
Positive phase data strobes for strand A to transfer data at the 2x
rate (800 MHz)
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description