Datasheet

Signal Description
2-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Scalability Port 0, 1 (continued)
SP{0/1}ASTBN[1:0]
I/O
SBD
400 MHz
N Strobes
Negative phase data strobes for strand A to transfer data at the 2x
rate (800 MHz)
SP{0/1}AD[15:0]
I/O
SBD
800 MHz
Data Bus
16 bits of the data portion of a phit on strand A. These bits are SSO
encoded. SP{0/1}ASSO determines if these are out of an inverter
or not.
SP{0/1}BD[15:0]=DATA[31:16].
SP{0/1}AEP[2:0]
I/O
SBD
800 MHz
Parity/ECC
Two of these signals carry the ECC information for the data
flits. There are four bits of ECC for each data phit. The header
flits are not ECC protected. The third signal is for parity. Each
phit is always protected by two bits of parity.
SP{0/1}AEP[1:0] = GEP[1:0]. AEP[2]=TEP[0].
SP{0/1}ALLC
I/O
SBD
800 MHz
Link Layer Control
For each PHIT these signals carry two of the four bits of link layer
control information.
SP{0/1}ASSO
I/O
SBD
800 MHz
SSO Encode
This signal is asserted to indicate that the data bits over Strand A
are inverted.
SP{0/1}ARSVD
I/O
SBD
800 MHz Reserved
SP{0/1}BVREFH[3:0]
I/O
Analog
N/A
Strand B Voltage reference
3/4 VCC Reference
SP{0/1}BVREFL[3:0]
I/O
Analog
N/A
Strand B Voltage Reference
1/4 VCC Reference
SP{0/1}BSTBP[1:0]
I/O
SBD
400 MHz
P Strobes
Positive phase data strobes for strand B to transfer data at the 2x
rate (800 MHz)
SP{0/1}BSTBN[1:0]
I/O
SBD
400 MHz
N Strobes
Negative phase data strobes for strand B to transfer data at the 2x
rate (800 MHz)
SP{0/1}BD[15:0]
I/O
SBD
800 MHz
Data Bus
16 bits of the data portion of a PHIT on strand B. These bits are
SSO encoded. SP{0/1}BSSO determines if these are out of an
inverter or not.
SP{0/1}BD[15:0]=DATA[31:16].
SP{0/1}BEP[2:0]
I/O
SBD
800 MHz
Parity/ECC
Two of these signals carry the ECC information for the data flits.
There are four bits of ECC for each data PHIT. The header flits are
not ECC protected. The third signal is for parity. Each PHIT is
always protected by two bits of parity.
SP{0/1}BEP[1:0] = GEP[3:2].
SP{0/1}BEP[2]=TEP[1].
SP{0/1}BLLC
I/O
SBD
800 MHz
Link Layer Control
For each PHIT these signals carry two of the four bits of link layer
control information.
SP{0/1}BSSO
I/O
SBD
800 MHz
SSO Encode
This signal is asserted to indicate that the data bits over Strand B
are inverted.
SP{0/1}BRSVD
I/O
SBD
800 MHz Reserved
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description