Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 2-5
Signal Description
Scalability Port 0, 1 (continued)
SP{0/1}GPIO[1:0]
I/O
CMOS1.5 OD
N/A
Scalability Port General Purpose I/O
These pins are asynchronous open drain I/O signals. To filter
glitches on the inputs, the value of the input only changes when
the same value has been sampled over four consecutive 200 MHz
clock cycles. Similarly, to ensure accurate sampling of these
signals by other devices, the output value will be asserted for a
minimum of 6 consecutive 200 MHz cycles.
LPC I/O Interface
LAD[3:0]
I/O
LPC
33 MHz
Multiplexed Address, Command and Data
LAD[3:0] are used to communicate:
• Start of a cycle
• Transfer type (Memory or I/O)
• Read or Write
• Address
• Data
• Stop (abort a cycle)
LFRAME#
O
LPC
33 MHz
Frame
SNC asserts this signal to indicate the start of a LPC or FWH cycle
and termination of an aborted cycle.
LRESET#
O
LPC
33 MHz
LPC Reset
LPC I/O reset. The SNC drives this signal during a hard reset to
initialize devices on the LPC interface.
LPCCLKOUT0
O
LPC
33 MHz
LPC Clock Out
Clock generated from the core clock to FWH or LPC device. This
signal trace is delay matched with the other two LPCCLKOUT
signals.
LPCCLKOUT1
O
LPC
33 MHz
LPC Clock Out
Clock generated from the core clock to FWH or LPC device. This
signal trace is delay matched with the other two LPCCLKOUT
signals.
LPCCLKOUT2
O
LPC
33 MHz
LPC Clock Out
Clock generated from the core clock to SNC. This signal trace is
delay matched with the two LPCCLKOUT signals and is connected
to the LCLK input.
LPCSEL
I
CMOS1.5
N/A
LPC/FWH Mode Select
When set to ‘1’ SNC generates LPC I/O reads and writes; when
set to ‘0’ SNC generated FWH I/O reads and writes.
LPCEN
I
CMOS1.5
N/A
LPC/FWH Present
When set to ‘1’ enables support of an LPC or FWH device attached
to the LPC I/O interface.
LCLK
I
LPC
33 MHz
LPC Clock In
Clock input for the LPC I/O interface that is asynchronous to the
SNC core clock This input may change asynchronous to BUSCLK.
Performance, Debug, and Error Signals
NODEID[4:0] /
DBG[4:0]#
I/O
CMOS1.5
N/A
NodeID
Strap bits that indicate the NodeID of this SNC. The NodeID is
captured on the rising edge of RESETI# and stored in the CBC
register. The captured value is sent on the IDLE flits. For E8870
chipset-based systems, NodeID[4:3] should always be set to “11”.
When the SNC is connected to switches other than the SPS,
NodeID[4:3] may be set to other values. For Itanium 2 processor-
based systems supporting the SAPIC model, each SNC must have
a unique NodeID. BusID is not examined when routing SAPIC
interrupts.
These signals should be pulled up or down with weak resistors that
will not draw more than the specified I
OL
or I
OH
of these signals
when they are driven with debug values after reset.
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description