Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 11-1
Testability 11
The SNC implements the Test Access Port (TAP) logic for testability purpose. The TAP complies
with the IEEE 1149.1 (JTAG) specification. Basic Functionality of the 1149.1-compatible test logic
is described here., but this document does not describe the IEEE 1149.1 standard in detail. For
details of the IEEE 1149.1 Specification, the reader is referred to the published standard
1
, and to
other industry standard material on the subject.
For specific boundary scan chain information, please reference the Intel SNC Boundary Scan
Descriptor Language (BSDL) Model.
11.1 Test Access Port (TAP)
Figure 11-1 illustrates the input and output signals for the TAP.
11.1.1 The TAP Logic
The TAP logic is accessed serially through 5 dedicated pins on each component shown in
Table 11-1.
TMS, TDI and TDO operate synchronously with TCK, which is independent of all other chipset
clocks. TRST# is an asynchronous input signal. This 5-pin interface operates as defined in the
1149.1 specification.
1. ANSI/IEEE Std. 1149.1-1990 (including IEEE Std. 1149.1a-1993), “IEEE Standard Test Access Port and Boundary Scan Architecture,”
IEEE Press, Piscataway NJ, 1993.
Figure 11-1. TAP Controller Signals
TDI
TMS
TCK
TRST#
TDO
Table 11-1. TAP Signal Definitions
TCK TAP Clock Input.
TMS Test Mode Select. Controls the TAP finite state machine.
TDI Test Data Input. The serial input for test instructions and data.
TDO Test Data Output. The serial output for the test data.
TRST# Test Reset Input.