Datasheet

Testability
11-2 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
A simplified block diagram of the TAP used in the this chipset components is shown in
Figure 11-2. This TAP logic consists of a finite state machine controller, a serially-accessible
instruction register, instruction decode logic, and data registers. The set of data registers includes
those described in the 1149.1 standard (the bypass register, device ID register, etc.), plus chipset-
specific additions. The private data registers used to control the test and debug features are not
shown.
11.1.2 Accessing the TAP Logic
The TAP is accessed through an IEEE 1149.1-compliant TAP controller finite state machine. This
finite state machine, shown in Figure 11-3, contains a reset state, a run-test/idle state, and two
major branches. These branches allow access either to the TAP Instruction Register or to one of the
data registers. The TMS pin is used as the controlling input to traverse this finite state machine.
TAP instructions and test data are loaded serially (in the Shift-IR and Shift-DR states, respectively)
using the TDI pin. State transitions are made on the rising edge of TCK.
The following is a brief description of each of the states of the TAP controller state machine. Refer
to the IEEE 1149.1 standard for detailed descriptions of the states and their operation.
• Test-Logic-Reset: In this state, the test logic is disabled so that the processor operates
normally. In this state, the instruction in the Instruction Register is forced to IDCODE.
Regardless of the original state of the TAP Finite State Machine (TAPFSM), it always enters
Test-Logic-Reset when the TMS input is held asserted for at least five clocks. The controller
also enters this state immediately when the TRST# pin is asserted, and automatically upon
power-on. The TAPFSM cannot leave this state as long as the TRST# pin is held asserted.
• Run-Test/Idle: A controller state between scan operations. Once entered the controller will
remain in this state as long as TMS is held low. In this state, activity in selected test logic
occurs only in the presence of certain instructions. For instructions that do not cause functions
to execute in this state, all test data registers selected by the current instructions retain their
previous state.
• Select-IR-Scan: This is a temporary controller state in which all test data registers selected by
the current instruction retain their previous state.
Figure 11-2. Simplified Block Diagram of TAP Controller
Device Identification
BYPASS Register
Instruction Register
TDI
TMS
TCK
TRST#
Control Logic
Instruction Decode /
Control Logic
Boundary Scan Register
Control Signals
TDO
TAP
Controller
Machine
TDO Mux