Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 11-3
Testability
• Capture-IR: In this state, the shift register contained in the Instruction Register loads a fixed
value (of which the two least significant bits are “01”) on the rising edge of TCK. The parallel,
latched output of the Instruction Register (current instruction) does not change in this state.
• Shift-IR: The shift register contained in the Instruction Register is connected between TDI
and TDO and is shifted one stage toward its serial output on each rising edge of TCK. The
output arrives at TDO on the falling edge of TCK. The current instruction does not change in
this state.
• Exit-IR: This is a temporary state and the current instruction does not change in this state.
• Pause-IR: Allows shifting of the Instruction Register to be temporarily halted. The current
instruction does not change in this state.
• Exit2-IR: This is a temporary state and the current instruction does not change in this state.
• Update-IR: The instruction which has been shifted into the Instruction Register is latched into
the parallel output of the Instruction Register on the falling edge of TCK. Once the new
instruction has been latched, it remains the current instruction until the next Update-IR (or
until the TAPFSM is reset).
Figure 11-3. TAP Controller State Diagram
000683
Select-
DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
0
0
1
0
1
1
1
0
0
0
Update-DR
1
Select-
IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
0
0
1
0
1
1
1
0
0
0
Update-IR
1
Run-Test/
Idle
Test-Logic-
Reset
0
11
00
1 TMS
1
0
1