Datasheet

Testability
11-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
• Select-DR-Scan: This is a temporary controller state and all test data registers selected by the
current instruction retain their previous values.
• Capture-DR: In this state, data may be parallel-loaded into test data registers selected by the
current instruction on the rising edge of TCK. If a test data register selected by the current
instruction does not have a parallel input, or if capturing is not required for the selected test,
then the register retains its previous state.
• Shift-DR: The data register connected between TDI and TDO as a result of selection by the
current instruction is shifted one stage toward its serial output on each rising edge of TCK. The
output arrives at TDO on the falling edge of TCK. If the data register has a latched parallel
output then the latch value does not change while new data is being shifted in.
• Exit1-DR: This is a temporary state and all data registers selected by the current instruction
retain their previous values.
• Pause-DR: Allows shifting of the selected data register to be temporarily halted without
stopping TCK. All registers selected by the current instruction retain their previous values.
• Exit2-DR: This is a temporary state and all registers selected by the current instruction retain
their previous values.
• Update-DR: Some test data registers may be provided with latched parallel outputs to prevent
changes in the parallel output while data is being shifted in the associated shift register path in
response to certain instructions. Data is latched into the parallel output of these registers from
the shift-register path on the falling edge of TCK.
11.2 Public TAP Instructions
Table 11-2 contains descriptions of the encoding and operation of the public TAP instructions.
There are four 1149.1-defined instructions implemented in this chipset device. These instructions
select from among three different TAP data registers – the boundary scan, device ID, and bypass
registers. The public instructions can be executed with only the standard connection of the JTAG
port pins. This means the only clock required will be TCK. Full details of the operation of these
instructions can be found in the 1149.1 standard. The opcodes are 1149.1-compliant, and are
consistent with the Intel-standard encodings.
A brief description of each instruction follows. For more thorough descriptions refer to the
IEEE 1149.1 specification.
Table 11-2. Public TAP Instructions
Instruction Encoding
Data Register
Selected
Description
BYPASS 1111111 Bypass
The BYPASS command selects the Bypass Register, a single bit
register connected between TDI and TDO pins. This allows more
rapid movement of test data to and from other components in the
system.
EXTEST 0000000
Boundary
Scan
The EXTEST Instruction allows circuitry or wiring external to the
devices to be tested. Boundary-Scan Register Cells at outputs
are used to apply stimulus while Boundary-Scan Cells at input
pins are used to capture data.