Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 11-5
Testability
11.3 Private TAP Instructions
Table 11-3 contains descriptions of the encoding and operation of the private, SNC TAP
instructions.
11.4 TAP registers
The following is a list of all test registers which can be accessed through the TAP.
1. Boundary Scan Register
The Boundary Scan register consists of several single-bit shift registers. The boundary scan
register provides a shift register path from all the input to the output pins on the SNC. Data is
transferred from TDI to TDO through the boundary scan register.
2. Bypass Register
The bypass register is a one-bit shift register that provides the minimal path length between
SAMPLE/
PRELOAD
0000001
Boundary
Scan
The SAMPLE/PRELOAD Instruction is used to allow scanning of
the boundary-scan register without causing interference to the
normal operation of the device. Two functions can be performed
by use of the Sample/Preload Instruction.
SAMPLE – allows a snapshot of the data flowing into & out of the
device to be taken without affecting the normal operation of the
device.
PRELOAD – allows an initial pattern to be placed into the
boundary-scan register cells. This allows initial known data to be
present prior to the selection of another boundary-scan test
operation.
IDCODE 0000010 IDCODE
The IDCODE instruction is forced into the parallel output latches
of the instruction register during the Test-Logic-Reset Tap state.
This allows the device identification register to be selected by
manipulation of the broadcast TMS and TCK signals for testing
purposes, as well as by a conventional instruction register scan
operation.
CLAMP 0000100
Boundary
Scan
This allows static "guarding values" to be set onto components
that are not specifically being tested while maintaining the
Bypass register as the serial path through the device.
HIGHZ 0001000
Boundary
Scan
The HIGHZ Instruction is used to force all outputs of the device
(except TDO) into a high impedance state. This instruction shall
select the Bypass Register to be connected between TDI and
TDO in the Shift-DR controller state.
Table 11-2. Public TAP Instructions (Continued)
Instruction Encoding
Data Register
Selected
Description
Table 11-3. Private TAP instructions
Instruction Binary Hex Description
JCONF
Config Access
1000010 42
This instruction is used to read or write configuration
registers in the chipset. Details of the bit definitions can be
found in section (Config Access Register).