Datasheet

Testability
11-6 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
TDI and TDO. The bypass register is selected when no test operation is being performed by a
component on the board. The bypass register loads a logic zero at the start of a scan cycle.
3. Device Identification (ID) Register
The device ID register contains the manufacturer’s identification code, version number, and
part number. The device ID register has a fixed length of 32 bits, as defined by the IEEE
1149.1 specification.
4. Instruction Register
This register consists of a 7-bit shift register (connected between TDI and TDO), and the
actual instruction register (which is loaded in parallel from the shift register). The parallel
output of the TAP instruction register goes to the TAP instruction decoder shown in
Figure 11-4.
5. Configuration Access Register
This register allows SNC to access the configuration registers via the JTAG TAP. An
acceptable configuration access chain format is shown.
Figure 11-4. TAP Instruction Register
LSB
MSB
Actual Instruction Register
Shift Register
Fixed Capture Value
TDOTDI
Parallel Output
Table 11-4. Example of Configuration Access Data Register Format
JCONF encode: 1000010
Bit Attr Default Description
63:56 RW 00h Data Byte3: MSB of the read/write data, Data[31:24]
55:48 RW 00h Data Byte2: Next MSB of the read/write data, Data[23:16]
47:40 RW 00h Data Byte1: Next LSB of the read/write data, Data[15:8]
39:32 RW 00h Data Byte0: LSB of the read/write data, Data[7:0]
31:24 RW 00h
Register Address:
Address of a register located in a device on a bus within a group of registers
assign to a function.
23:19 RW 00h
Device ID:
PCI equivalent to uniquely identify a device on a bus.
18:16 RW 000
Function Number:
PCI equivalent of a function number to obtain access to register banks within a
device.
15:8 RW 00h
Bus Number:
PCI equivalent of a bus number to recognize devices connected to this bus.