Datasheet

Signal Description
2-6 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Performance, Debug, and Error Signals (continued)
BUSID[2:0] /
DBG[7:5]#
I/O
CMOS1.5
N/A
BusID
Strap bits that indicate the configuration bus number of this SNC.
These bits are captured by the CBC register on the rising edge of
RESETI#. The captured value is sent on the IDLE flits.
For E8870 chipset systems, BusID should always be set to “111”.
When the SNC is used with switches other than the SPS, BusID
may be set to other values.
These signals should be pulled up or down with weak resistors that
will not draw more than the specified I
OL
or I
OH
of these signals
when they are driven with debug values after reset.
DBG[7:0]# N/A
Debug Bus
These bits form part of an 8-bit debug bus. Once the NodeID is
captured after hard reset, debug signals selected by the DEVT
register may be driven on these signals.
INT_OUT#
O
CMOS1.5 OD
200 MHz
Interrupt Request
This signal is asserted by SNC when the SPINCO register sets a
flag that has been configured to request an interrupt. The SNC
drives this signal for a minimum of 6 cycles.
BINITIN#
I
CMOS1.5
200 MHz
Assert BINIT
This signal is driven by the system logic. When asserted, the SNC
should drive BINIT# on the processor bus according to protocol.
This signal must be sampled at the same value four consecutive
cycles before changing state. This input may change
asynchronous to BUSCLK.
BERRIN#
I
CMOS1.5
200 MHz
Assert BERR
This signal is driven by the system logic. When asserted, the SNC
should drive BERR# on the processor bus according to protocol.
This signal must be sampled at the same value four consecutive
cycles before changing state. This input may change
asynchronous to BUSCLK.
BINITOUT#
O
CMOS3.3
200 MHz
Processor asserted BINIT
The SNC asserts this signal for at least 12 cycles when BINIT# is
sampled asserted, but not driven by the SNC.
BERROUT#
O
CMOS3.3
200 MHz
Processor asserted BERR
The SNC asserts this signal for at least 12 cycles when BERR# is
sampled asserted, but not driven by the SNC.
ERR[2:0]#
I/O
CMOS1.5 OD
200 MHz
Error Code
The SNC drives and samples error information on these signals.
• ERR[0] is asserted for correctable errors.
• ERR[1] is asserted for non-correctable errors.
• ERR[2] is asserted for fatal errors.
The FERRST register samples these signals up till the cycle
before the SNC drives. The SNC drives these for a minimum of 12
cycles. The input must be sampled at the same value four
consecutive cycles before changing state.This input may change
asynchronous to BUSCLK.
EV[3:0]#
I/O
CMOS1.5 OD
200 MHz
Events
These signals are driven and sampled by performance monitoring
and debug logic. The SNC drives these for a minimum of 12
cycles. The input must be sampled at the same value four
consecutive cycles before changing state.This input may change
asynchronous to BUSCLK.
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description