Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 2-7
Signal Description
Clocking
BUSCLK
I
Differential
200 MHz
Bus Clock
This is one of the two differential reference clock inputs to the
Phase Locked Loop (PLL) in the SNC core. The circuit board
transmission line driving this signal must be delay-matched to the
corresponding processor clock signal generated by the system
board logic.
BUSCLK#
I
Differential
200 MHz
Bus Clock Complement
This is the other one of the two differential reference clock inputs to
the PLL in the SNC core. The circuit board transmission line
driving this signal must be delay-matched to the corresponding
processor clock signal generated by the system board logic.
VCCAFSB
I
Analog
N/A
VCC
PLL Analog Voltage for the processor bus PLL.
VCCASP
I
Analog
N/A
VCC
PLL Analog Voltage for the SP PLL.
VCCACORE
I
Analog
N/A
VCC
PLL Analog Voltage for the core PLL.
VSSAFSB
I
Analog
N/A
VSS
PLL Analog Ground for the processor bus PLL.
VSSASP
I
Analog
N/A
VSS
PLL Analog Ground for the SP PLL.
VSSACORE
I
Analog
N/A
VSS
PLL Analog Ground for the core PLL.
System Management
SPDCLK
I/O
CMOS3.3 OD
SPDCLK SMBus for Serial Presence Detect Clock. Unused.
SPDDA
I/O
CMOS3.3 OD
SPDCLK SMBus for Serial Presence Detect Address/Data. Unused.
SCL
I/O
CMOS3.3 OD
SCL
SMBus Clock
This input may change asynchronous to BUSCLK.
SDA
I/O
CMOS3.3 OD
SCL
SMBus Address/Data
This input may change asynchronous to BUSCLK.
TDIOANODE
I/O
Analog
N/A
Thermal Diode Anode
This is the anode of the thermal diode.
TDIOCATHODE
I/O
Analog
N/A
Thermal Diode Cathode
This is the cathode of the thermal diode.
Reset
CPUPRES#
I
CMOS1.5
N/A
CPU Present
When asserted, at least one CPU is present. Requires external
pull-up. This is tied to all CPUPRES# signals of the Itanium 2
processor socket.
PWRGOOD
I
CMOS1.5
N/A
Power Good
Clears the SNC. This signal is held low until all power supplies are
in specification. This signal may be pulsed after power-up to
completely reset the SNC.
RESETI#
I
CMOS1.5
N/A
Reset Input
This is the hard reset input to the SNC. This input may change
asynchronous to BUSCLK.
RESET#
O
AGTL+
N/A
CPU Reset
This signal is the processor bus reset. Asserted due to RESETI#,
or writes to SYRE register.
RESETO#
O
CMOS1.5
N/A
Reset Output
Asserted when system hard reset field in SYRE register is written.
May be routed by the system to the component that asserts reset.
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description