Datasheet

Signal Description
2-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Reset (continued)
MEMRST0#
O
CMOS1.8
N/A
Memory Subsystem Reset
This signal is asserted by SNC to reset the DMHs (DDR Memory
Hubs). It is pulsed just after the deassertion of RESETI#. This is
pulsed on every SNC RESETI# deassertion.
MEMRST1#
O
CMOS1.8
N/A
Memory Subsystem Reset
This is the same as MEMRST0#. This is used so that MEMRST0#
is not overloaded.
COMPCNTRL[1:0]#
I
CMOS1.5
N/A
Bit 0 :ITPODTDIS#
On-die-termination disable on RESET# and BPM[5:0]#, to allow
connection of an In-Target-Probe to those processor bus pins.
Bit 1 :COMPCNTRL[1]#
Enables glitch filters on STBP[7:0]# and STBN[7:0]#. Recommend
being able to strap either way.
FSBSLWCRES[1:0]
I
Analog
N/A
Compensation Resistors
Compensation Resistors for the processor bus slew rate.
FSBODTCRES[1:0]
I
Analog
N/A
Compensation Resistors
Compensation Resistors for the processor bus on-die termination.
RACODTCRES[1:0]
I
Analog
N/A
Compensation Resistors
Compensation Resistors for the RAC on-die termination.
RACODTEN[1:0]
I
CMOS1.5
N/A
On-die Termination
RAC on-die termination enable.
LVHSTLODTEN
I
CMOS1.5
N/A
On-die Termination
BUSCLK and BUSCLK# on-die termination enable.
Power
VTTMK
I
Analog
N/A
Itanium 2 Processor Bus Termination Voltage
(67 occurrences)
VCCSP
I
Analog
N/A
Scalability Port Supply Voltage
(34 occurrences)
VCCRIO
I
Analog
N/A
RAMBUS Termination Voltage
(24 occurrences)
VCCRA
I
Analog
N/A
RAC DLL Supply Voltage
(8 occurrences)
VCC3.3LPC
I
Analog
N/A
LPC I/O Supply Voltage
(2 occurrences)
VCCI2C
I
Analog
N/A SMB and miscellaneous 3.3-volt I/O supply voltage.
Test Access Port (JTAG)
TCK
I
JTAG
TCK
JTAG Test Clock
Clock input used to drive Test Access Port (TAP) state machine
during test and debugging. This input may change asynchronous
to BUSCLK.
TDI
I
JTAG
TCK
JTAG Test Data In
Data input for test mode. Used to serially shift data and instructions
into TAP.
TDO
O
JTAG
TCK
JTAG Test Data Out
Data output for test mode. Used to serially shift data out of the TAP.
TMS
I
JTAG
TCK
JTAG Test Mode Select
This signal is used to control the state of the TAP controller.
TRST#
I
JTAG
N/A
JTAG Test Reset
This signal resets the TAP controller logic. It should be pulled down
unless TCK is active. This input may change asynchronous to
BUSCLK.
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description