Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 2-9
Signal Description
Itanium
®
2 Processor Bus
A[43:3]#
I/O
AGTL+
200 MHz
Address Signals
Processor Address Bus. During processor cycles these are inputs.
SNC drives A[43:3]# for transactions originating from SP and for
deferred reply transactions.
ADS#
I/O
AGTL+
200 MHz
Address/Data Strobe
Indicates the first cycle of any request phase. This signal is driven
and sampled by SNC.
AP[1:0]#
I/O
AGTL+
200 MHz
Address Parity
Parity protection on the address bus. SNC will generate AP[1:0]#
for its own transactions. SNC will also monitor AP[1:0]# for all
transactions and check parity on the address bus.
BERR#
I/O
AGTL+
200 MHz
Bus Error
BERR# indicates unrecoverable bus protocol violation. SNC will
sample and drive BERR#. SNC will drive BERR# according to the
protocol when the signal BERRIN gets asserted.
BINIT#
I/O
AGTL+
200 MHz
Bus Initialization
This signal is asserted to reinitialize bus state machines. SNC will
terminate any ongoing transactions at this time. This signal does
not affect the state of configuration registers and error logging
registers.
BNR#
I/O
AGTL+
200 MHz
Block Next Request
SNC will assert this signal when it runs out of internal resources
while a locked transaction is in progress. SNC may also assert this
signal during a hard reset sequence. SNC will also monitor this
signal when driven by a processor to block any of its transactions
from being issued on the bus.
SNC asserts BNR# for debug.
BPM[5:0]#
I/O
AGTL+
200 MHz
Breakpoint/Debug Bus
This group of signals is used by the system debug logic and SNC
for communicating debug information. SNC drives BPM[3:0]# and
BPM[5]#. BPM[4]# is not driven by SNC.
BPRI#
O
AGTL+
200 MHz
Priority Agent Bus Request
SNC asserts this signal to drive requests originating from SP and
to issue a deferred reply transaction in some special cases. SNC
will also assert this signal to block the processors from issuing
transactions. BPRI# assertion will have the same effect as BNR#
assertion in this case with the exception that SNC will drive its
snoop requests on the processor bus. Symmetric agents do not
drive this signal. This signal is sampled by SNC internally.
BREQ0#
I/O
AGTL+
200 MHz
Physical Bus Request
SNC drives BREQ[0]# during reset and deasserts it one clock after
SNC samples reset deasserted.
BREQ[3:1]#
I
AGTL+
200 MHz
Physical Bus Request
SNC does not drive BREQ[3:1]#. SNC observes active
BREQ[3:0]# from processors to determine deassertion of BPRI# to
transfer bus ownership to the processor.
D[127:0]#
I/O
AGTL+
400 MHz
Data Bus
128 bits of data driven by the agent responsible for driving the data
during the Data phase.
DBSY#
I/O
AGTL+
200 MHz
Data Bus Busy
Indicates that the data bus is owned by the agent responsible for
driving the data during the Data phase. DBSY# assertion does not
imply that data is being transferred that cycle.
DEFER#
O
AGTL+
200 MHz
Defer
SNC asserts DEFER# for all processor initiated transactions with
DEN# on. SNC will also generate deferred responses for these
transactions except for the cases when an in-order retry is forced.
Table 2-4. SNC Signal List (Continued)
Signal Type Frequency Description