Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheetiii
Contents
1 Introduction......................................................................................................................1-1
1.1 Overview ............................................................................................................1-1
1.2 Scalable Node Controller (SNC) Overview ........................................................1-1
1.3 Architectural Overview .......................................................................................1-3
1.4 Interfaces............................................................................................................1-4
1.4.1 Intel
®
Itanium
®
2 Processor System Bus ..............................................1-4
1.4.2 Main Channel ........................................................................................1-4
1.4.3 Scalability Port (SP) Interface ...............................................................1-5
1.4.4 Low Pin Count/Firmware Hub Interface ................................................1-5
1.4.5 JTAG Interface ......................................................................................1-5
1.4.6 SMBus Slave Interface..........................................................................1-6
1.5 Terminology........................................................................................................1-6
1.6 References.........................................................................................................1-8
1.7 Revision History .................................................................................................1-8
2 Signal Description ...........................................................................................................2-1
2.1 Conventions .......................................................................................................2-1
2.2 SNC Signal List ..................................................................................................2-2
3 Configuration Registers...................................................................................................3-1
3.1 Access Mechanisms...........................................................................................3-1
3.2 SNC Fixed Memory Mapped Registers..............................................................3-1
3.2.1 SPADA: Scratch Pad Alias....................................................................3-2
3.2.2 SPADSA: Sticky Scratch Pad Alias.......................................................3-2
3.2.3 BOFLA: Boot Flag Alias ........................................................................3-2
3.2.4 CBCA1: Chip Boot Configuration Alias .................................................3-2
3.2.5 CBCA2: Chip Boot Configuration Alias .................................................3-2
3.2.6 CBCA3: Chip Boot Configuration Alias .................................................3-3
3.3 SNC I/O Space Registers...................................................................................3-3
3.3.1 CFGADR: Configuration Address Register ...........................................3-3
3.3.2 CFGDAT: Configuration Data Register .................................................3-4
3.4 SNC Configuration Registers .............................................................................3-4
3.5 PCI Standard Registers......................................................................................3-4
3.5.1 VID: Vendor Identification Register .......................................................3-4
3.5.2 DID: Device Identification Register........................................................3-5
3.5.3 CCR: Class Code Register....................................................................3-5
3.5.4 RID: Revision Identification Register.....................................................3-6
3.5.5 HDR: Header Type Register .................................................................3-6
3.5.6 SVID: Subsystem Vendor Identification Register..................................3-6
3.5.7 SID: Subsystem Identity........................................................................3-7
3.6 Address Mapping Registers ...............................................................................3-7
3.6.1 MAR[5:0]: Memory Attribute Region Registers .....................................3-7
3.6.2 ASE: Address Space Enable Register ..................................................3-8
3.6.3 MMIOH: High Memory Mapped I/O Space Register .............................3-8
3.6.4 MMIOL: Low Memory Mapped I/O Space Register...............................3-9
3.6.5 AGP1: Advanced Graphics Port Sub-Range 1 Register .....................3-10
3.6.6 MMCFG: Memory Mapped Configuration Space Register..................3-10
3.6.7 IORD: I/O Redirection Register...........................................................3-11