Datasheet
Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-1
Configuration Registers 3
3.1 Access Mechanisms
The SNC configuration registers can be accessed from the following sources:
• Configuration Read and Write from either scalability port (SP)
• System Management Bus (SMBus)
• JTAG
:
3.2 SNC Fixed Memory Mapped Registers
These registers are mapped into the “SNC Memory Mapped Configuration Register Range” shown
in Table 4-6, “Address Disposition for Processor.” These appear at fixed addresses to support the
boot process. These registers also appear in the SNC configuration space. This mechanism is
independent of the more general Memory Mapped Configuration mechanism.
Table 3-1. Register Attributes Definitions
Attribute
Abbrevi-
ation
Description
Read Only RO
The bit is set by the hardware only and software can only read the bit.
Writes to the register have no effect. A hard reset will set the bit to its default
value.
Read/Write RW
The bit can be read and written by software. A hard reset will set the bit to its
default value.
Read/Write
Once
RWO
The bit can be read by software. It can also be written by software but the
hardware prevents writing it more than once without a prior reset. Since the
smallest register access is one byte, this protection applies on a byte-by-
byte basis. That is, if only one byte of a field is written, only that byte will be
locked. The other byte has separate write protection.
Read/Clear RC
The bit can be either read or cleared by software. In order to clear an RC bit,
the software must write a one to it. Writing a zero to an RC bit will have no
effect. A hard reset will set the bit to its default value.
Sticky
RWS, RCS,
ROS
The bit is “sticky” or unchanged by a hard reset. Read/Write, Read/Clear,
and Read Only bits may be sticky. These bits are only reset with
PWRGOOD.
Reserved RV
This bit is reserved for future expansion and must not be written. The PCI
Local Bus Specification, Revision 2.2 requires that reserved bits must be
preserved. Any software that modifies a register that contains a reserved bit
is responsible for reading the register, modifying the desired bits, and writing
back the result.
Unique *
Any attribute with an asterisk (*) suffix indicates an unique behavior. Please
consult the associated description for details.