Datasheet

Configuration Registers
3-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.3.2 CFGDAT: Configuration Data Register
CFGDAT provides data for the four bytes of configuration space defined by CFGADR. This
register is only accessed if there is an access to I/O address CFCh on the processor bus and
CFGADR.CFGE is set. The byte enables with the I/O access define how many configuration bytes
are accessed.
3.4 SNC Configuration Registers
The SNC is viewed by the system as a single PCI device with four different functions. Offsets 0 to
40h are used for the standard PCI header as defined in PCI Local Bus Specification, Rev. 2.2.
Table 3-2 lists the configuration address maps for each function of the SNC.
Configuration reads to other functions return all 1’s. Reads to undefined (reserved) registers return
all 0’s. Writes to other functions and undefined registers are dropped.
3.5 PCI Standard Registers
3.5.1 VID: Vendor Identification Register
This register identifies Intel as the manufacturer of the SNC. Writes to this register have no effect.
I/O Address:CFCh
Bit Attr Default Description
31:0 RW 0
Configuration Data Window
The data written or read to the configuration register (if any) specified by
CFGADR.
Table 3-2. Register Grouping by Function
Function Types of Registers
0 Processor bus control.
1 Memory controller.
2 Scalability Port 0 and registers common to both SPs.
3 Scalability Port 1 and global performance monitoring.
Device: NodeID
Function: 0,1,2,3
Offset: 00 - 01h
Bit Attr Default Description
15:0 RO 8086h
Vendor Identification Number
This is the standard 16-bit value assigned to Intel.