Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-7
Configuration Registers
3.5.7 SID: Subsystem Identity
This register identifies the system.
3.6 Address Mapping Registers
3.6.1 MAR[5:0]: Memory Attribute Region Registers
This register defines the memory attributes on the 11 memory segments in the 512 Kbyte to
1 MByte address range. These attributes determine whether the SNC routes a processor request to
main memory or to the compatibility bus. The SNC takes no special action if the request is to be
routed to memory. If the request is to be routed to the compatibility bus, it is directed out to the
scalability port as if it were a remote memory read, but with a attribute field set to CB. Each
register holds the attributes for two segments (see Table 4-6 “Address Disposition for Processor” ).
Table 3-3 shows the MAR registers and the associated attribute bits.
Software on Itanium 2 processors must map C_0000-F_FFFFh to main memory for the SNC.
Device: Node_ID
Function: 0, 1, 2, 3
Offset: 2Eh
Bit Attr Default Description
15:0 RWO 8086h
Subsystem Identification Number
The default value specifies Intel as the system ID for the SNC. Each byte of this
register will be writable once. Second and successive writes to a byte will have no
effect.
Device: NodeID
Function: 0
Offset: 54h, 55h, 56h, 57h, 58h, 59h
Bit Attr Default Description
7:6 RV 0 Reserved
5RW0
WE1: Segment 1, Write Enable
When set, route write requests to main memory. Otherwise, route to
compatibility bus.
4RW0
RE1: Segment 1, Read Enable
When set, route write requests to main memory. Otherwise, route to
compatibility bus.
3:2 RV 0 Reserved
1RW0
WE0: Segment 0, Write Enable
When set, route write requests to main memory. Otherwise, route to
compatibility bus.
0RW0
RE0: Segment 0, Read Enable
When set, route write requests to main memory. Otherwise, route to
compatibility bus.