Datasheet

Configuration Registers
3-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.6.2 ASE: Address Space Enable Register
This register defines the Video Graphics Adapter and Monochrome Display Address ranges.
Table 4-6 define the usage of these bits.
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3.6.3 MMIOH: High Memory Mapped I/O Space Register
This register defines the High Memory Mapped I/O space. It starts at FF_FFFF_FFFFh and
extends downward in 4-GB increments to a minimum lower limit of 1_0000_0000h.
Table 3-3. MAR Register Mappings
Register Bits Attribute Bits Memory Segment Default
MAR0 (54h)
3:0 Reserved 0
7:4 ––WE RE 0F0000h - 0FFFFFh 0
MAR1 (55h)
3:0 ––WE RE 0C0000h - 0C3FFFh 0
7:4 ––WE RE 0C4000h - 0C7FFFh 0
MAR2 (56h)
3:0 ––WE RE 0C8000h - 0CBFFFh 0
7:4 ––WE RE 0CC000h - 0CFFFFh 0
MAR3 (57h)
3:0 ––WE RE 0D0000h - 0D3FFFh 0
7:4 ––WE RE 0D4000h - 0D7FFFh 0
MAR4 (58h)
3:0 ––WE RE 0D8000h - 0DBFFFh 0
7:4 ––WE RE 0DC000h - 0DFFFFh 0
MAR5 (59h)
3:0 ––WE RE 0E0000h - 0E7FFFh 0
7:4 ––WE RE 0E8000h - 0EFFFFh 0
Device: NodeID
Function: 0
Offset: 5Bh
Bit Attr Default Description
7:3 RV 0 Reserved
2RW0
ISAEN: ISA Aliasing Enable
If set, I/O addresses X100 - X3FFh, X500 - X7FFh, X900 - XBFFh, and
XD00 - XFFFh may be redirected to compatibility bus.
1RW0
MDASE: Monochrome Display Adapter Space Enable
This bit affects the attribute field and request type applied to outbound SP
requests for memory addresses in the range B_0000 - B_7FFFh and I/O
requests to 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh.
0RW0
VGASE: VGA I/O Space Enable
This bit affects the attribute field and request type applied to outbound SP
requests for memory addresses in the range (A_0000 - B_FFFFh) and I/O
addresses in the (03B0h - 03BBh and 03C0h - 03DFh) ranges.