Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-9
Configuration Registers
Processor requests to this space are directed to a particular SP port as a function of the SPINCO
and AGP1 registers. This routing forces a single path to each Memory Mapped I/O location. This
enables writes to be pipelined while maintaining sequential order.
Processor requests to this range are non-coherent. Non-coherent Read/Write are issued on the SP.
An address is in the High MMIO space if:
• (A[43:40] = 0h) AND (A[39:32] > BASE)
3.6.4 MMIOL: Low Memory Mapped I/O Space Register
This register defines the Low Memory Mapped I/O space. It starts at FDFF_FFFFh and extends
downward in 16MB increments to a minimum value of 64MB. This region is described in “High
and Low Memory Mapped I/O (MMIO)” in Chapter 4, “System Address Map.”
Processor requests to this space are directed to a particular SP port as a function of the SPINCO
and AGP1 registers. This routing forces a single path to each Memory Mapped I/O location. This
enables writes to be pipelined while maintaining sequential order.
Processor requests to this range are non-coherent. Non-coherent Read/Write are issued on the SP.
The memory behind this range can be recovered using reflection. The SNC will not scrub any
memory mapped to this range and will only scrub the memory recovered from this range in MIRs
with the RFLCT bit set. See Section 5.2.1, “Scrub Address Generation.”
An address is in the Low MMIO space if:
• (A[43:32] = 000h) AND (FDh >= A[31:24] > BASE)
Device: NodeID
Function: 0
Offset: 60h
Bit Attr Default Description
15:8 RV 0 Reserved
7:0 RW FFh
BASE
Defines the lower limit of High MMIO range. These bits are compared against
A[39:32]. This field is one less than A[39:32] for the lowest address in the High
MMIO range. If FFh, this range is disabled. This register should be set to the
same value as the MMIOBH register in the SIOH.
Device: NodeID
Function: 0
Offset: 64h
Bit Attr Default Description
15:8 RV 0 Reserved
7:0 RW FFh
BASE
Defines the lower limit of the Low MMIO range. These bits are compared
against A[31:24]. This field is one less than A[31:24] for the lowest address in
the Low MMIO range. If >= FDh, this range is disabled. This register should be
set to the same value as the MMIOBL register in the SIOH.