Datasheet

iv Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.6.8 SMRAM: SMM RAM Control Register.................................................3-11
3.6.9 MIR[9:0]: Memory Interleave Range Registers ...................................3-12
3.7 Memory Controller Registers ...........................................................................3-13
3.7.1 MC: Memory Control Settings .............................................................3-13
3.7.2 MIT[9:0]: Memory Interleave Technology Registers............................3-14
3.7.3 STM: DDR-SDRAM Timing Register...................................................3-16
3.7.4 DRC: DRAM Maintenance Control Register .......................................3-18
3.7.5 RCD: RAMBUS* Configuration Data Register ....................................3-19
3.7.6 SCC: DDR SDRAM Configuration Command Register.......................3-19
3.7.7 MTS: Memory Test and Scrub Register..............................................3-21
3.7.8 XTPR[7:0]: External Task Priority Register.........................................3-22
3.8 Reset, Boot and Control Registers...................................................................3-23
3.8.1 SYRE: System Reset ..........................................................................3-23
3.8.2 CVDR: Configuration Values Driven on Reset....................................3-23
3.8.3 CVCR: Configuration Values Captured on Reset................................3-25
3.8.4 SPAD: Scratch Pad.............................................................................3-26
3.8.5 SPADS: Sticky Scratch Pad................................................................3-26
3.8.6 BOFL: Boot Flag .................................................................................3-27
3.8.7 CBC: Chip Boot Configuration ............................................................3-27
3.8.8 SPC: Scalability Port Control Register ................................................3-28
3.8.9 FSBC: Processor Bus Control Register ..............................................3-29
3.8.10 FWHSEL: FWH Device Select............................................................3-29
3.8.11 SNCINCO: SNC Interface Control.......................................................3-30
3.8.12 SP0INCO, SP1INCO: SP Interface Control ........................................3-31
3.9 Error Registers .................................................................................................3-33
3.9.1 ERRCOM: Error Command.................................................................3-33
3.9.2 FERRST: First Error Status.................................................................3-33
3.9.3 SERRST: Second Error Status ...........................................................3-38
3.9.4 ERRMASK: ERRST MASK .................................................................3-38
3.9.5 RECFSB: Recoverable Error Control Information of
Processor Bus.....................................................................................3-39
3.9.6 NRECFSB: Non-recoverable Error Control Information of
Processor Bus.....................................................................................3-40
3.9.7 RECSPP: Recoverable Error Control Information of SPP...................3-41
3.9.8 NRECSPP: Non-recoverable Error Control Information of SPP..........3-41
3.9.9 RED: Non-Fatal Error Data Log ..........................................................3-41
3.9.10 REDSPL[1:0]: SP Non-fatal Error Data Log........................................3-42
3.9.11 RECSPL[1:0]: Recoverable Error Control Information of SP[1:0] .......3-42
3.9.12 RECMEM: Recoverable Error Control Information of Memory............3-43
3.9.13 REDMEM: Memory Read Data Error Log...........................................3-43
3.10 Performance Monitoring Registers...................................................................3-44
3.10.1 PERFCON: Performance Monitor Master Control...............................3-44
3.10.2 PTCTL: Timer Control .........................................................................3-46
3.10.3 PMINIT: Timer Initial Value Register...................................................3-48
3.10.4 PMTIM: Timer Current Value ..............................................................3-48
3.10.5 FSBPMD[1:0]: Processor Bus Performance Monitor Data..................3-48
3.10.6 FSBPMC[1:0]: Processor Bus Performance Compare........................3-48
3.10.7 FSBPMR[1:0]: Processor Bus Performance Monitor Response .........3-49
3.10.8 FSBPMEL[1:0]: Processor Bus Performance Monitor Events LO.......3-52
3.10.9 FSBPMEH[1:0]: Processor Bus Performance Monitor Events HI .......3-53
3.10.10 FSBPMER[1:0]: Processor Bus Performance Monitor
Resource Events.................................................................................3-54