Datasheet

Configuration Registers

3-10 Intel

E8870 Scalable Node Controller (SNC) Datasheet

3.6.5 AGP1: Advanced Graphics Port Sub-Range 1 Register

In general, transactions to the High and Low MMIO range are routed out the default SP. This

non-default SP to balance loading. An enabled AGP1 range must be configured to fall within either

the High or Low MMIO range (see Section 3.6.3, “MMIOH: High Memory Mapped I/O Space

this range is considered null.

An address falls in AGP1 range if:

HI/LO AND A[43:40]=0h AND (MMIOH.BAS <= AGP1.BAS < A[39:32] <= AGP1.LIM) OR

!HI/LO AND A[43:32] =000h AND (MMIOL.BAS <= AGP1.BAS < A[31:24] <= AGP1.LIM <= FDh)

3.6.6 MMCFG: Memory Mapped Configuration Space Register

This register defines the Memory Mapped Configuration space. This space maps the entire PCI

configuration space into memory. This space is relocatable in 64 MB increments above 4 GB

(1_0000_0000h). It may not overlap MMIOH. It may not overlap High MMIO or any other space.

To avoid race conditions, software may only modify this register by CF8/CFC. Software must also

guarantee that there is no race between issue of MMCFG requests and changes in this register. That

is, all MMCFG accesses that expect the old register value must be completed before any write to

this register is issued, and the register write must complete on the processor bus before any

MMCFGs are issued that expect the new register value. See Table 4-8, “Address Disposition for

Inbound Transactions.”

The address of requests in this range are compared against CBC.NodeID and CBC.Bus to

determine whether the request accesses registers on this SNC. If not, it is converted into a non-

coherent configuration Read/Write and issued on one of the SPs.

An address is in the MMCFG space if:

• The space is enabled: (BASE > 03Fh)

• A[43:26] == BASE

Device: NodeID

Function: 0

Offset: 4C-4Eh

Bit Attr Default Description

24:16 RV 0 Reserved

16 RW 0

HI/LO

If set, the AGP1 range falls in the High MMIO range. Otherwise it falls in the

low MMIO range. If in the high range, AGP1_LIM and AGP1_BASE are

compared against A[39:32], otherwise A[31:24].

15:8 RW 0

LIM

This field specifies the upper limit for the AGP1 sub-range within an MMIO

region. This field is A[39:32] (High MMIO) or A[31:24] (Low MMIO) for the

highest address in the AGP1 range.

7:0 RW 0

BAS

This field specifies the lower limit for the AGP1 sub-range within an MMIO

region. This field is one less than A[39:32] (High MMIO) or A[31:24] (Low

MMIO) address bits for the lowest address in the AGP1 range.