Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-11
Configuration Registers
3.6.7 IORD: I/O Redirection Register
This register is used to redirect I/O segments to the compatibility PCI bus. Certain I/O addresses
(e.g. MDA,VGA,CFC/CF8) are not redirected according to this register. Section 4.3.2.1,
“Outbound I/Os” defines the types of I/O accesses that are not governed by this register. Each bit in
this register corresponds with a 4-KB I/O segment.
3.6.8 SMRAM: SMM RAM Control Register
This register must be programmed consistently with the SMRAM register in the SIOH. As the
Itanium 2 processor does not support SMM, undefined system operation will result if this register
is written. The default value leaves SMM space disabled.
Device: NodeID
Function: 0
Offset: 50h
Bit Attr Default Description
31:18 RV 0 Reserved
17:0 RW 0
BASE
Defines the lower limit of MMCFG range. These bits are compared against
A[43:26]. If less than 40h, this range is disabled.
Device: NodeID
Function: 0
Offset: 68h
Bit Attr Default Description
15:0 RW 0
I/O Redirection Bits
Each bit corresponds with a 4-KB I/O segment. Bit 0 corresponds with the
lowest 4 KBs, Bit 1 corresponds with the next 4 KBs, etc. If an IORD bit is
asserted, requests to the corresponding addresses will have a Attr field of the
SP I/O Read/Write request be set to CB.
Device: NodeID
Function: 0
Offset: 5C - 5Fh
Bit Attr Default Description
31:0 RV 0 Reserved