Datasheet

Configuration Registers
3-12 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.6.9 MIR[9:0]: Memory Interleave Range Registers
These registers define 10 ranges in which all the main memory supported by this SNC falls.
Collectively, all the MIRs that cover a range and the Memory Interleave Technology (MIT)
associated with them define a cache line interleave. The cache line interleave is the repeating
sequence of channels, devices, and internal banks over which a linear stream of cache line accesses
cycle.
The MIRs on an SNC define whether an access is directed to local memory or sent to a scalability
port switch for further routing. The MIRs on the SP switch define the SNC that services each cache
line of memory. There is not a 1:1 association of SP switch MIRs with SNC MIRs. Multiple SNC
MIRs may cover the same range as one way of an SP switch MIR. One SNC MIR may describe a
contiguous address range covered by a series of SP switch MIRs.
All the memory covered by an SNC MIR must be the same technology. There is one Memory
Interleave Technology (MIT) Register in each SNC associated with each MIR. The MIT defines
the number of rows, columns, and banks addressed. The MIR and MIT jointly define how cache
lines are interleaved across devices, channels, and banks.
To support interleave across different technologies, up to four MIRs on the same or different SNCs
may be set to the same address range. The ways field of each MIR is used to divide cache lines
among the MIRs sharing an address range. Each MIR may cover 1, 2, or 4 ways. The remainder of
the 32-way interleave is across devices, banks, or channels of identical technology as defined by
the MIT registers and the address bit assignments in Section 5.3.2.5, “DDR Address Bit Mapping.”
The WAYS, BASE and SIZE fields define the existence and extent of this interleave. An address
falls in this interleave if:
• WAYS [A[8:7]] AND [BASE <= A[43:27] < BASE + 2
SIZE
]
Device: NodeID
Function: 1
Offset: 60h,64h,68h,6Ch,70h,74h,78h,7Ch,C4h,C8h
Bit Attr Default Description
31:26 RV 0 Reserved
25:9 RW 0
BASE
This defines the lowest address in the interleave. These bits are compared
against A[43:27]. This field must be set to a multiple of the Interleave size
defined below.
8:4 RW 0
SIZE
2
SIZE
is the number of 128-MB blocks in the interleave range. To describe all
the memory supported by a given set of devices. For example, for DDR this
field should be set according to the contents of the MIT register with the same
index as follows:
MIR[i].SIZE = 32B (bytes per quantum) • 4 (Banks) • MIT[i].NUMROW •
MIT[i].NUMCOL • MIT[i].SIDES • MIR[i].W • MIT[i].DIV
Where MIR[i].W is 4 divided by the number of ones in the WAYS field, below.
(This memory can also be divided among multiple MIRs covering different
ranges.) MIT[i].DIV should be interpreted to have values 1, 1/2, or 1/4. The
MIR used to recover memory by reflection will not follow the equation above. It
should have a size field as small as possible to cover maximum anticipated
expansion of the reflected region.