Datasheet
Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-13
Configuration Registers
3.7 Memory Controller Registers
3.7.1 MC: Memory Control Settings
3:0 RW 0
WAYS
If the bit in this field selected by A[8:7] is set, the access is sent to the devices
described by the corresponding MIT register. Each way bit of every Memory
Interleave Range must be set in exactly one MIR.
[3] = Selected if A[8:7] = 11
[2] = Selected if A[8:7] = 10
[1] = Selected if A[8:7] = 01
[0] = Selected if A[8:7] = 00
Any MIR can cover 1, 2, or 4 ways of an interleave. Only certain combinations
are consistent with the address bit mapping described in Table 5-5 “DDR
Address Bit Mapping” and Table 5-6, “Interleave Field Mapping for DDR.”
0000 Range disabled: This SNC has no memory in this range.
0001 This MIR decodes way 0 - (A[8:7]=00)
0010 This MIR decodes way 1 - (A[8:7]=01
0100 This MIR decodes way 2 - (A[8:7]=10)
1000 This MIR decodes way 3 - (A[8:7]=11)
0101 This MIR decodes way 0 and 2 - (A[7]=0)
1010 This MIR decodes way 1 and 3 - (A[7]=1)
1111 This MIR decodes all ways in this range.
Device: NodeID
Function: 1
Offset: 40h
Bit Attr Default Description
15:13 RV 0 Reserved
12 RW 0
RROE: DDR Read to Read Optimization
0 = STM.Trr determines the spacing between any read on the same DDR
channel. This setting must be used when some DRAM devices do not
support concurrent auto-precharge. The lack of concurrent auto-
precharge support can be inferred from DRAM specification that mention
an “access period” following RDA or WRA.
1 = Back-to-back Reads can be made to the same DDR device. STM.Trr
determines the spacing between reads to different devices on the same
DDR channel.
11:8 RV 0 Reserved
7RW0
MWBL: Minimum Write Burst Length Enable
The minimum number of writes required for issue. Prior to normal operation,
this bit should be 0, so that all writes flush in the absence of reads. In normal
operation, this bit should be set to 1 so that incoming reads are not delayed by
write unnecessary write flushes.
0 = Writes are issued in the absence of reads
1 = Writes are not issued unless four are posted. Up to three posted writes
may persist in the SNC indefinitely.
Device: NodeID
Function: 1
Offset: 60h,64h,68h,6Ch,70h,74h,78h,7Ch,C4h,C8h (Continued)
Bit Attr Default Description