Datasheet

Configuration Registers
3-14 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
3.7.2 MIT[9:0]: Memory Interleave Technology Registers
These registers define the mapping of address bits to DDR channels, devices, internal banks, rows,
and columns for this node. Each MIT groups together similar devices to maximize interleave
across channels, devices and banks.
There is one MIT for each memory range defined by the MIRs. All devices covered by one MIT
must be the same size and technology. If the ways field of the associated MIR indicates that this
interleave is disabled, the settings of this MIT are not applied.
6RW0
MECBD: Memory Error Correction Bypass Disable
0 = Normal Operation: Correction path is not taken unless correction is
required.
1 = All data is forced through the correction path.
5RW0
MECE: Memory Error Correction Enable
0 = No memory read errors are corrected. Logging is unaffected, but
poisoning will not occur. Good SEC/DED will be generated for all memory
reads.
1 = Enable Error correction (see Section 5.2, “Error Correction”). This bit
should not be set if MECBD=1.
4RW1
MT: Memory Type
0 = Reserved
1 = Synchronous DDR DRAM.
3:0 RV 0 Reserved
Device: NodeID
Function: 1
Offset: 40h (Continued)
Bit Attr Default Description
Table 3-4. MIT Definition for DDR SDRAM
Device: NodeID
Function: 1
Offset: A0h,A4h,A8h,ACh,B0h,B4h,B8h,BCh,CCh,D0h
Bit Attr Default Description
31:19 RV 0 Reserved
18 RW 0
RFLCT: MIR used for Reflection
If set, this Memory Interleave Range is used to recover memory behind
MMIOL. In this MIR, the SNC will only scrub locations in the recovered range
(see Section 5.2.1, “Scrub Address Generation”). If this bit is set, the
corresponding MIR.SIZE may not cover the entire DIMM, but should be 4GB
maximum.
17:15 RV 0 Reserved
14 RW 0
Channel
Defines the DDR channel this DIMM occupies. Modifies the Channel number
in the MCP.