Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 3-15
Configuration Registers
13:11 RW 0
RAFIX
This field defines which portion of the DIMM is mapped by this register. This is
accomplished by assigning fixed values to the most significant Row address
bits for this technology. The same half or quarter of a DIMM should not be
mapped by different MITs. Table 5-7 “MCP Bits Forced by RAFIX and DIV
Fields for DIMM Splitting” defines how this affects address bit mapping.
0 = This MIR/MIT maps the first quarter or first half of the DIMM
1 = This MIR/MIT maps the second quarter of the DIMM
2 = This MIR/MIT maps the third quarter or second half of the DIMM
3 = This MIR/MIT maps the fourth quarter of the DIMM
10:9 RW 0
ROW
Defines the Chip Selects (CS) connected to this DIMM. Together with the
SIDES field, determines the chip select fields in the MCP. Single-sided DIMMs
are only connected to the first CS of the pair.
0 = CS0 and CS1
1 = CS2 and CS3
2 = CS4 and CS5
3 = CS6 and CS7
8RV0 Reserved
7RW0
SIDES
Defines the number of sides this DIMM has. Modifies the Interleave field
mapping to ping-pong across Chip Selects as defined in Table 5-6, “Interleave
Field Mapping for DDR.”
0 = single-sided
1 = double-sided
6:5 RW 0
DIV
This field can be set to split a DIMM among 2, 3, or 4 MIR/MIT pairs. The
different portions can be assigned to independent address ranges as defined
by the RAFIX field. Table 5-7 “MCP Bits Forced by RAFIX and DIV Fields for
DIMM Splitting” defines how this affects address bit mapping.
0 = This MIR/MIT maps the entire DIMM
1=Reserved
2 = This MIR/MIT maps 1/2 of the DIMM
3 = This MIR/MIT maps 1/4 of the DIMM
4:3 RW 0
NUMROW: Technology – Number of Rows
The number of rows within the devices of this interleave. See Section 5-4,
“Bits Used in MCP Packet for Different DDR Technologies” for legal
combinations with other fields.
0 = 4096
1 = 8192
2 = 16384
2:0 RW 0
NUMCOL: Technology – Number of Columns
The number of columns within the devices of this interleave.See Section 5-4
for legal combinations with other Technology fields.
0 = 512
1 = 1024
2 = 2048
3 = 4096
4 = 8192
Table 3-4. MIT Definition for DDR SDRAM (Continued)
Device: NodeID
Function: 1
Offset: A0h,A4h,A8h,ACh,B0h,B4h,B8h,BCh,CCh,D0h (Continued)
Bit Attr Default Description