Datasheet
Configuration Registers
3-16 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
A MIT may not describe more than one DIMM. Multiple MITs can apply to the same DIMM if the
associated MIR registers define different address ranges.
The DMH specifies the correlation between CS to SPD address bits on DIMMs and the format of
the Memory Control Packets (MCP).
3.7.3 STM: DDR-SDRAM Timing Register
This register defines timing parameters that work with all DDR SDRAMs in the memory
subsystem. The parameters for these devices can be obtained by serial presence detect (see
Section 3.7.5, “RCD: RAMBUS* Configuration Data Register”). This register must be set to
provide timings that satisfy the specifications of all DRAMs detected. If DRAMs present have
different Tcas, the maximum should be used to program this register.
Consult DDR SDRAM specifications for the technology of the devices in use. Consult the North-
bridge Levelization Procedure section of the Intel
®
E8870DH DDR Memory Hub (DMH)
Datasheet for procedures to set these timing parameters.
Device: NodeID
Function: 1
Offset: C0h
Bit Attr Default Description
31 RV 0 Reserved
30:27 RW 2h
TRD: Read MCP to Data Delay
TRD defines the delay from the beginning of a read/write MCP to first data
sample in RClk resolution.
Read to data delay = 2 •
t
RD
+20; (20-46)
Write to data delay = 2 •
t
RD
+17; (17-43)
legal values are 0000 through 1101
The
tcwd (DMH Main channel Write delay) parameter in the DMH should be
set to 2 •
t
RD
+13.
26:22 RV 0 Reserved
21:20 RW 3h
TRQ: RAC RQ Transmit Timing
Selects one of the four programmable timing points within SyncClk period
(10ns) for transmitting RQ. The four timing points are identical to the Tselect
timing in the Direct RAC Data Sheet. TRQ should always be set to 11.
0 0 Reserved
0 1 Reserved
1 0 Reserved
1 1 Transmit RQData with Tselect = 1000 timing
19:18 RW 2h
TRW: Read to Write Delay
The minimum delay from the Read command to the next Write command on
the same branch DDR channel. This parameter is varied to avoid data strobe
protocol violations on the DIMM data bus. Table 3-5 defines the settings of this
parameter as a function of DMH parameters.
0 0 30 ns
0 1 40 ns
1 0 50 ns
1 1 60 ns